186 lines
5.6 KiB
C
186 lines
5.6 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_ace_intc
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/devicetree/interrupt_controller.h>
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#include <zephyr/irq_nextlevel.h>
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#include <zephyr/arch/xtensa/irq.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/drivers/interrupt_controller/dw_ace.h>
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#include <soc.h>
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#include <adsp_interrupt.h>
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#include <zephyr/irq.h>
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#include "intc_dw.h"
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/* ACE device interrupts are all packed into a single line on Xtensa's
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* architectural IRQ 4 (see below), run by a Designware interrupt
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* controller with 28 lines instantiated. They get numbered
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* immediately after the Xtensa interrupt space in the numbering
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* (i.e. interrupts 0-31 are Xtensa IRQs, 32 represents DW input 0,
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* etc...).
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*
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* That IRQ 4 indeed has an interrupt type of "EXTERN_LEVEL" and an
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* interrupt level of 2. The CPU has a level 1 external interrupt on
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* IRQ 1 and a level 3 on IRQ 6, but nothing seems wired there. Note
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* that this level 2 ISR is also shared with the CCOUNT timer on IRQ3.
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* This interrupt is a very busy place!
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*
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* But, because there can never be a situation where all interrupts on
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* the Synopsys controller are disabled (such a system would halt
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* forever if it reached idle!), we at least can take advantage to
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* implement a simplified masking architecture. Xtensa INTENABLE
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* always has the line active, and we do all masking of external
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* interrupts on the single controller.
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*
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* Finally: note that there is an extra layer of masking on ACE. The
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* ACE_DINT registers provide separately maskable interrupt delivery
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* for each core, and with some devices for different internal
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* interrupt sources. Responsibility for these mask bits is left with
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* the driver.
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*
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* Thus, the masking architecture picked here is:
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*
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* + Drivers manage ACE_DINT themselves, as there are device-specific
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* mask indexes that only the driver can interpret. If
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* core-asymmetric interrupt routing needs to happen, it happens
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* here.
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*
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* + The DW layer is en/disabled uniformly across all cores. This is
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* the layer toggled by arch_irq_en/disable().
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*
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* + Index 4 in the INTENABLE SR is set at core startup and stays
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* enabled always.
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*/
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/* ACE also has per-core instantiations of a Synopsys interrupt
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* controller. These inputs (with the same indices as ACE_INTL_*
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* above) are downstream of the DINT layer, and must be independently
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* masked/enabled. The core Zephyr intc_dw driver unfortunately
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* doesn't understand this kind of MP implementation. Note also that
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* as instantiated (there are only 28 sources), the high 32 bit
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* registers don't exist and aren't named here. Access via e.g.:
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*
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* ACE_INTC[core_id].irq_inten_l |= interrupt_bit;
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*/
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#define ACE_INTC ((volatile struct dw_ictl_registers *)DT_INST_REG_ADDR(0))
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static inline bool is_dw_irq(uint32_t irq)
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{
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if (((irq & XTENSA_IRQ_NUM_MASK) == ACE_INTC_IRQ)
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&& ((irq & ~XTENSA_IRQ_NUM_MASK) != 0)) {
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return true;
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}
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return false;
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}
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void dw_ace_irq_enable(const struct device *dev, uint32_t irq)
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{
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ARG_UNUSED(dev);
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if (is_dw_irq(irq)) {
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unsigned int num_cpus = arch_num_cpus();
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for (int i = 0; i < num_cpus; i++) {
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ACE_INTC[i].irq_inten_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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ACE_INTC[i].irq_intmask_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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}
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} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
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xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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}
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}
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void dw_ace_irq_disable(const struct device *dev, uint32_t irq)
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{
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ARG_UNUSED(dev);
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if (is_dw_irq(irq)) {
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unsigned int num_cpus = arch_num_cpus();
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for (int i = 0; i < num_cpus; i++) {
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ACE_INTC[i].irq_inten_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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ACE_INTC[i].irq_intmask_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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}
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} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
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xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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}
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int dw_ace_irq_is_enabled(const struct device *dev, unsigned int irq)
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{
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ARG_UNUSED(dev);
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if (is_dw_irq(irq)) {
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return ACE_INTC[0].irq_inten_l & BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
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return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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}
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return false;
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}
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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int dw_ace_irq_connect_dynamic(const struct device *dev, unsigned int irq,
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unsigned int priority,
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void (*routine)(const void *parameter),
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const void *parameter, uint32_t flags)
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{
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/* Simple architecture means that the Zephyr irq number and
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* the index into the ISR table are identical.
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*/
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ARG_UNUSED(dev);
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ARG_UNUSED(flags);
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ARG_UNUSED(priority);
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z_isr_install(irq, routine, parameter);
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return irq;
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}
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#endif
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static void dwint_isr(const void *arg)
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{
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uint32_t fs = ACE_INTC[arch_proc_id()].irq_finalstatus_l;
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while (fs) {
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uint32_t bit = find_lsb_set(fs) - 1;
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uint32_t offset = CONFIG_2ND_LVL_ISR_TBL_OFFSET + bit;
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struct _isr_table_entry *ent = &_sw_isr_table[offset];
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fs &= ~BIT(bit);
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ent->isr(ent->arg);
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}
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}
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static int dw_ace_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(ACE_INTC_IRQ, 0, dwint_isr, 0, 0);
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xtensa_irq_enable(ACE_INTC_IRQ);
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return 0;
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}
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static const struct dw_ace_v1_ictl_driver_api dw_ictl_ace_v1x_apis = {
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.intr_enable = dw_ace_irq_enable,
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.intr_disable = dw_ace_irq_disable,
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.intr_is_enabled = dw_ace_irq_is_enabled,
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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.intr_connect_dynamic = dw_ace_irq_connect_dynamic,
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#endif
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};
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DEVICE_DT_INST_DEFINE(0, dw_ace_init, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY,
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&dw_ictl_ace_v1x_apis);
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IRQ_PARENT_ENTRY_DEFINE(ace_intc, DEVICE_DT_INST_GET(0), DT_INST_IRQN(0),
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INTC_BASE_ISR_TBL_OFFSET(DT_DRV_INST(0)),
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DT_INST_INTC_GET_AGGREGATOR_LEVEL(0));
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