46 lines
1.0 KiB
Plaintext
46 lines
1.0 KiB
Plaintext
# CAVS interrupt controller configuration
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config CAVS_ICTL
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bool "CAVS Interrupt Logic"
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default y
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depends on DT_HAS_INTEL_CAVS_INTC_ENABLED
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depends on MULTI_LEVEL_INTERRUPTS
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help
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These are 4 in number supporting a max of 32 interrupts each.
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if CAVS_ICTL
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config CAVS_ISR_TBL_OFFSET
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int "Offset in the SW ISR Table"
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default 0
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help
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This indicates the offset in the SW_ISR_TABLE beginning from where
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the ISRs for CAVS Interrupt Controller are assigned.
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config CAVS_ICTL_0_OFFSET
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int "Parent interrupt number to which CAVS_0 maps"
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default 0
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config CAVS_ICTL_1_OFFSET
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int "Parent interrupt number to which CAVS_1 maps"
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default 0
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config CAVS_ICTL_2_OFFSET
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int "Parent interrupt number to which CAVS_2 maps"
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default 0
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config CAVS_ICTL_3_OFFSET
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int "Parent interrupt number to which CAVS_3 maps"
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default 0
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config CAVS_ICTL_INIT_PRIORITY
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int "CAVS ICTL Init priority"
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default 45
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help
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Cavs Interrupt Logic initialization priority.
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endif # CAVS_ICTL
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