462 lines
13 KiB
C
462 lines
13 KiB
C
/*
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* Copyright 2023 NXP
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* Copyright 2023 CogniPilot Foundation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_tja1103
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#include <errno.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/net/phy.h>
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#include <zephyr/net/mii.h>
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#include <zephyr/net/mdio.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(phy_tja1103, CONFIG_PHY_LOG_LEVEL);
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/* PHYs out of reset check retry delay */
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#define TJA1103_AWAIT_DELAY_POLL_US 15000U
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/* Number of retries for PHYs out of reset check */
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#define TJA1103_AWAIT_RETRY_COUNT 200U
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/* TJA1103 PHY identifier */
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#define TJA1103_ID 0x1BB013
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/* MMD30 - Device status register */
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#define TJA1103_DEVICE_CONTROL (0x0040U)
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#define TJA1103_DEVICE_CONTROL_GLOBAL_CFG_EN BIT(14)
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#define TJA1103_DEVICE_CONTROL_SUPER_CFG_EN BIT(13)
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/* Shared - PHY control register */
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#define TJA1103_PHY_CONTROL (0x8100U)
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#define TJA1103_PHY_CONTROL_CFG_EN BIT(14)
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/* Shared - PHY status register */
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#define TJA1103_PHY_STATUS (0x8102U)
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#define TJA1103_PHY_STATUS_LINK_STAT BIT(2)
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/* Shared - PHY functional IRQ masked status register */
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#define TJA1103_PHY_FUNC_IRQ_MSTATUS (0x80A2)
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#define TJA1103_PHY_FUNC_IRQ_LINK_EVENT BIT(1)
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#define TJA1103_PHY_FUNC_IRQ_LINK_AVAIL BIT(2)
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/* Shared -PHY functional IRQ source & enable registers */
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#define TJA1103_PHY_FUNC_IRQ_ACK (0x80A0)
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#define TJA1103_PHY_FUNC_IRQ_EN (0x80A1)
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#define TJA1103_PHY_FUNC_IRQ_LINK_EVENT_EN BIT(1)
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#define TJA1103_PHY_FUNC_IRQ_LINK_AVAIL_EN BIT(2)
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/* Always accessible reg for NMIs */
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#define TJA1103_ALWAYS_ACCESSIBLE (0x801F)
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#define TJA1103_ALWAYS_ACCESSIBLE_FUSA_PASS_IRQ BIT(4)
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struct phy_tja1103_config {
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const struct device *mdio;
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struct gpio_dt_spec gpio_interrupt;
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uint8_t phy_addr;
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uint8_t master_slave;
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};
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struct phy_tja1103_data {
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const struct device *dev;
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struct phy_link_state state;
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struct k_sem sem;
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struct k_sem offload_sem;
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phy_callback_t cb;
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struct gpio_callback phy_tja1103_int_callback;
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void *cb_data;
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K_KERNEL_STACK_MEMBER(irq_thread_stack, CONFIG_PHY_TJA1103_IRQ_THREAD_STACK_SIZE);
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struct k_thread irq_thread;
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struct k_work_delayable monitor_work;
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};
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static inline int phy_tja1103_c22_read(const struct device *dev, uint16_t reg, uint16_t *val)
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{
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const struct phy_tja1103_config *const cfg = dev->config;
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return mdio_read(cfg->mdio, cfg->phy_addr, reg, val);
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}
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static inline int phy_tja1103_c22_write(const struct device *dev, uint16_t reg, uint16_t val)
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{
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const struct phy_tja1103_config *const cfg = dev->config;
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return mdio_write(cfg->mdio, cfg->phy_addr, reg, val);
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}
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static inline int phy_tja1103_c45_write(const struct device *dev, uint16_t devad, uint16_t reg,
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uint16_t val)
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{
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const struct phy_tja1103_config *cfg = dev->config;
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return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);
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}
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static inline int phy_tja1103_c45_read(const struct device *dev, uint16_t devad, uint16_t reg,
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uint16_t *val)
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{
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const struct phy_tja1103_config *cfg = dev->config;
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return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);
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}
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static int phy_tja1103_reg_read(const struct device *dev, uint16_t reg_addr, uint32_t *data)
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{
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const struct phy_tja1103_config *cfg = dev->config;
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int ret;
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mdio_bus_enable(cfg->mdio);
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ret = phy_tja1103_c22_read(dev, reg_addr, (uint16_t *)data);
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mdio_bus_disable(cfg->mdio);
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return ret;
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}
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static int phy_tja1103_reg_write(const struct device *dev, uint16_t reg_addr, uint32_t data)
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{
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const struct phy_tja1103_config *cfg = dev->config;
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int ret;
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mdio_bus_enable(cfg->mdio);
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ret = phy_tja1103_c22_write(dev, reg_addr, (uint16_t)data);
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mdio_bus_disable(cfg->mdio);
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return ret;
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}
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static int phy_tja1103_id(const struct device *dev, uint32_t *phy_id)
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{
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uint16_t val;
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if (phy_tja1103_c22_read(dev, MII_PHYID1R, &val) < 0) {
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return -EIO;
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}
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*phy_id = (val & UINT16_MAX) << 16;
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if (phy_tja1103_c22_read(dev, MII_PHYID2R, &val) < 0) {
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return -EIO;
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}
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*phy_id |= (val & UINT16_MAX);
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return 0;
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}
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static int update_link_state(const struct device *dev)
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{
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struct phy_tja1103_data *const data = dev->data;
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bool link_up;
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uint16_t val;
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if (phy_tja1103_c45_read(dev, MDIO_MMD_VENDOR_SPECIFIC1, TJA1103_PHY_STATUS, &val) < 0) {
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return -EIO;
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}
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link_up = (val & TJA1103_PHY_STATUS_LINK_STAT) != 0;
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/* Let workqueue re-schedule and re-check if the
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* link status is unchanged this time
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*/
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if (data->state.is_up == link_up) {
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return -EAGAIN;
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}
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data->state.is_up = link_up;
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return 0;
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}
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static int phy_tja1103_get_link_state(const struct device *dev, struct phy_link_state *state)
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{
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struct phy_tja1103_data *const data = dev->data;
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const struct phy_tja1103_config *const cfg = dev->config;
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int rc = 0;
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k_sem_take(&data->sem, K_FOREVER);
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/* If Interrupt is configured then the workqueue will not
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* update the link state periodically so do it explicitly
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*/
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if (cfg->gpio_interrupt.port != NULL) {
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rc = update_link_state(dev);
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}
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memcpy(state, &data->state, sizeof(struct phy_link_state));
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k_sem_give(&data->sem);
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return rc;
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}
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static void invoke_link_cb(const struct device *dev)
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{
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struct phy_tja1103_data *const data = dev->data;
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struct phy_link_state state;
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if (data->cb == NULL) {
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return;
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}
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/* Send callback only on link state change */
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if (phy_tja1103_get_link_state(dev, &state) != 0) {
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return;
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}
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data->cb(dev, &state, data->cb_data);
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}
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static void monitor_work_handler(struct k_work *work)
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{
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struct k_work_delayable *dwork = k_work_delayable_from_work(work);
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struct phy_tja1103_data *const data =
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CONTAINER_OF(dwork, struct phy_tja1103_data, monitor_work);
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const struct device *dev = data->dev;
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int rc;
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k_sem_take(&data->sem, K_FOREVER);
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rc = update_link_state(dev);
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k_sem_give(&data->sem);
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/* If link state has changed and a callback is set, invoke callback */
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if (rc == 0) {
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invoke_link_cb(dev);
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}
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/* Submit delayed work */
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k_work_reschedule(&data->monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
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}
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static void phy_tja1103_irq_offload_thread(void *p1, void *p2, void *p3)
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{
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ARG_UNUSED(p2);
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ARG_UNUSED(p3);
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const struct device *dev = p1;
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struct phy_tja1103_data *const data = dev->data;
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uint16_t irq;
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for (;;) {
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/* await trigger from ISR */
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k_sem_take(&data->offload_sem, K_FOREVER);
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if (phy_tja1103_c45_read(dev, MDIO_MMD_VENDOR_SPECIFIC1,
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TJA1103_PHY_FUNC_IRQ_MSTATUS, &irq) < 0) {
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return;
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}
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/* Handling Link related Functional IRQs */
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if (irq & (TJA1103_PHY_FUNC_IRQ_LINK_EVENT | TJA1103_PHY_FUNC_IRQ_LINK_AVAIL)) {
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/* Send callback to MAC on link status changed */
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invoke_link_cb(dev);
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/* Ack the assered link related interrupts */
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phy_tja1103_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC1,
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TJA1103_PHY_FUNC_IRQ_ACK, irq);
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}
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}
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}
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static void phy_tja1103_handle_irq(const struct device *port, struct gpio_callback *cb,
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uint32_t pins)
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{
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ARG_UNUSED(pins);
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ARG_UNUSED(port);
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struct phy_tja1103_data *const data =
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CONTAINER_OF(cb, struct phy_tja1103_data, phy_tja1103_int_callback);
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/* Trigger BH before leaving the ISR */
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k_sem_give(&data->offload_sem);
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}
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static void phy_tja1103_cfg_irq_poll(const struct device *dev)
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{
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struct phy_tja1103_data *const data = dev->data;
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const struct phy_tja1103_config *const cfg = dev->config;
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int ret;
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if (cfg->gpio_interrupt.port != NULL) {
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if (!gpio_is_ready_dt(&cfg->gpio_interrupt)) {
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LOG_ERR("Interrupt GPIO device %s is not ready",
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cfg->gpio_interrupt.port->name);
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return;
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}
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ret = gpio_pin_configure_dt(&cfg->gpio_interrupt, GPIO_INPUT);
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if (ret < 0) {
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LOG_ERR("Failed to configure interrupt GPIO, %d", ret);
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return;
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}
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gpio_init_callback(&(data->phy_tja1103_int_callback), phy_tja1103_handle_irq,
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BIT(cfg->gpio_interrupt.pin));
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/* Add callback structure to global syslist */
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ret = gpio_add_callback(cfg->gpio_interrupt.port, &data->phy_tja1103_int_callback);
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if (ret < 0) {
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LOG_ERR("Failed to add INT callback, %d", ret);
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return;
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}
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ret = phy_tja1103_c45_write(
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dev, MDIO_MMD_VENDOR_SPECIFIC1, TJA1103_PHY_FUNC_IRQ_EN,
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(TJA1103_PHY_FUNC_IRQ_LINK_EVENT_EN | TJA1103_PHY_FUNC_IRQ_LINK_AVAIL_EN));
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if (ret < 0) {
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return;
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}
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ret = gpio_pin_interrupt_configure_dt(&cfg->gpio_interrupt, GPIO_INT_EDGE_FALLING);
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if (ret < 0) {
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LOG_ERR("Failed to enable INT, %d", ret);
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return;
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}
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/* PHY initialized, IRQ configured, now initialize the BH handler */
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k_thread_create(&data->irq_thread, data->irq_thread_stack,
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CONFIG_PHY_TJA1103_IRQ_THREAD_STACK_SIZE,
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phy_tja1103_irq_offload_thread, (void *)dev, NULL, NULL,
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CONFIG_PHY_TJA1103_IRQ_THREAD_PRIO, K_ESSENTIAL, K_NO_WAIT);
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k_thread_name_set(&data->irq_thread, "phy_tja1103_irq_offload");
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} else {
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k_work_init_delayable(&data->monitor_work, monitor_work_handler);
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monitor_work_handler(&data->monitor_work.work);
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}
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}
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static int phy_tja1103_cfg_link(const struct device *dev, enum phy_link_speed adv_speeds)
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{
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ARG_UNUSED(dev);
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if (adv_speeds & LINK_FULL_100BASE_T) {
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return 0;
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}
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return -ENOTSUP;
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}
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static int phy_tja1103_init(const struct device *dev)
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{
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const struct phy_tja1103_config *const cfg = dev->config;
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struct phy_tja1103_data *const data = dev->data;
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uint32_t phy_id = 0;
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uint16_t val;
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int ret;
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data->dev = dev;
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data->cb = NULL;
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data->state.is_up = false;
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data->state.speed = LINK_FULL_100BASE_T;
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ret = WAIT_FOR(!phy_tja1103_id(dev, &phy_id) && phy_id == TJA1103_ID,
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TJA1103_AWAIT_RETRY_COUNT * TJA1103_AWAIT_DELAY_POLL_US,
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k_sleep(K_USEC(TJA1103_AWAIT_DELAY_POLL_US)));
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if (ret < 0) {
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LOG_ERR("Unable to obtain PHY ID for device 0x%x", cfg->phy_addr);
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return -ENODEV;
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}
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/* enable config registers */
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ret = phy_tja1103_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC1, TJA1103_DEVICE_CONTROL,
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TJA1103_DEVICE_CONTROL_GLOBAL_CFG_EN |
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TJA1103_DEVICE_CONTROL_SUPER_CFG_EN);
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if (ret < 0) {
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return ret;
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}
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ret = phy_tja1103_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC1, TJA1103_PHY_CONTROL,
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TJA1103_PHY_CONTROL_CFG_EN);
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if (ret < 0) {
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return ret;
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}
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ret = phy_tja1103_c45_read(dev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, &val);
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if (ret < 0) {
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return ret;
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}
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/* Change master/slave mode if need */
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if (cfg->master_slave == 1) {
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val |= MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
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} else if (cfg->master_slave == 2) {
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val &= ~MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
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}
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ret = phy_tja1103_c45_write(dev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, val);
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if (ret < 0) {
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return ret;
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}
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/* Check always accesible register for handling NMIs */
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ret = phy_tja1103_c45_read(dev, MDIO_MMD_VENDOR_SPECIFIC1, TJA1103_ALWAYS_ACCESSIBLE, &val);
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if (ret < 0) {
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return ret;
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}
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/* Ack Fusa Pass Interrupt if Startup Self Test Passed successfully */
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if (val & TJA1103_ALWAYS_ACCESSIBLE_FUSA_PASS_IRQ) {
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ret = phy_tja1103_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC1,
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TJA1103_ALWAYS_ACCESSIBLE,
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TJA1103_ALWAYS_ACCESSIBLE_FUSA_PASS_IRQ);
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}
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/* Configure interrupt or poll mode for reporting link changes */
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phy_tja1103_cfg_irq_poll(dev);
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return ret;
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}
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static int phy_tja1103_link_cb_set(const struct device *dev, phy_callback_t cb, void *user_data)
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{
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struct phy_tja1103_data *const data = dev->data;
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data->cb = cb;
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data->cb_data = user_data;
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/* Invoke the callback to notify the caller of the current
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* link status.
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*/
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invoke_link_cb(dev);
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return 0;
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}
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static const struct ethphy_driver_api phy_tja1103_api = {
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.get_link = phy_tja1103_get_link_state,
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.cfg_link = phy_tja1103_cfg_link,
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.link_cb_set = phy_tja1103_link_cb_set,
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.read = phy_tja1103_reg_read,
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.write = phy_tja1103_reg_write,
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};
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#define TJA1103_INITIALIZE(n) \
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static const struct phy_tja1103_config phy_tja1103_config_##n = { \
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.phy_addr = DT_INST_REG_ADDR(n), \
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.mdio = DEVICE_DT_GET(DT_INST_BUS(n)), \
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.gpio_interrupt = GPIO_DT_SPEC_INST_GET_OR(n, int_gpios, {0}), \
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.master_slave = DT_INST_ENUM_IDX(n, master_slave), \
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}; \
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static struct phy_tja1103_data phy_tja1103_data_##n = { \
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.sem = Z_SEM_INITIALIZER(phy_tja1103_data_##n.sem, 1, 1), \
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.offload_sem = Z_SEM_INITIALIZER(phy_tja1103_data_##n.offload_sem, 0, 1), \
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}; \
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DEVICE_DT_INST_DEFINE(n, &phy_tja1103_init, NULL, &phy_tja1103_data_##n, \
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&phy_tja1103_config_##n, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY, \
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&phy_tja1103_api);
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DT_INST_FOREACH_STATUS_OKAY(TJA1103_INITIALIZE)
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