375 lines
11 KiB
C
375 lines
11 KiB
C
/*
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* Copyright 2020,2023-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_pit
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/irq.h>
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#include <fsl_pit.h>
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#define LOG_MODULE_NAME counter_pit
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL);
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/* Device holds a pointer to pointer to data */
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#define PIT_CHANNEL_DATA(dev) \
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(*(struct nxp_pit_channel_data *const *const)dev->data)
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/* Device config->data is an array of data pointers ordered by channel number,
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* dev->data is a pointer to one of these pointers in that array,
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* so the value of the dev->data - dev->config->data is the channel index
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*/
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#define PIT_CHANNEL_ID(dev) \
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(((struct nxp_pit_channel_data *const *)dev->data) - \
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((const struct nxp_pit_config *)dev->config)->data)
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struct nxp_pit_channel_data {
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uint32_t top;
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counter_top_callback_t top_callback;
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void *top_user_data;
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};
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struct nxp_pit_config {
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struct counter_config_info info;
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PIT_Type *base;
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bool enableRunInDebug;
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int num_channels;
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#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
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void (*irq_config_func)(const struct device *dev);
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#else
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void (**irq_config_func)(const struct device *dev);
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#endif
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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struct nxp_pit_channel_data *const *data;
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const struct device *const *channels;
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};
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static uint32_t nxp_pit_get_top_value(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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pit_chnl_t channel = PIT_CHANNEL_ID(dev);
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/*
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* According to RM, the LDVAL trigger = clock ticks -1
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* The underlying HAL driver function PIT_SetTimerPeriod()
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* automatically subtracted 1 from the value that ends up in
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* LDVAL so for reporting purposes we need to add it back in
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* here to by consistent.
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*/
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return (config->base->CHANNEL[channel].LDVAL + 1);
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}
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static int nxp_pit_start(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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int channel_id = PIT_CHANNEL_ID(dev);
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LOG_DBG("period is %d", nxp_pit_get_top_value(dev));
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PIT_EnableInterrupts(config->base, channel_id,
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kPIT_TimerInterruptEnable);
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PIT_StartTimer(config->base, channel_id);
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return 0;
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}
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static int nxp_pit_stop(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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int channel_id = PIT_CHANNEL_ID(dev);
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PIT_DisableInterrupts(config->base, channel_id,
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kPIT_TimerInterruptEnable);
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PIT_StopTimer(config->base, channel_id);
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return 0;
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}
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static int nxp_pit_get_value(const struct device *dev, uint32_t *ticks)
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{
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const struct nxp_pit_config *config = dev->config;
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int channel_id = PIT_CHANNEL_ID(dev);
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*ticks = PIT_GetCurrentTimerCount(config->base, channel_id);
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return 0;
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}
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static int nxp_pit_set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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const struct nxp_pit_config *config = dev->config;
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struct nxp_pit_channel_data *data = PIT_CHANNEL_DATA(dev);
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pit_chnl_t channel = PIT_CHANNEL_ID(dev);
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if (cfg->ticks == 0) {
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return -EINVAL;
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}
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data->top_callback = cfg->callback;
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data->top_user_data = cfg->user_data;
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if (config->base->CHANNEL[channel].TCTRL & PIT_TCTRL_TEN_MASK) {
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/* Timer already enabled, check flags before resetting */
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if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
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return -ENOTSUP;
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}
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PIT_StopTimer(config->base, channel);
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PIT_SetTimerPeriod(config->base, channel, cfg->ticks);
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PIT_StartTimer(config->base, channel);
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} else {
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PIT_SetTimerPeriod(config->base, channel, cfg->ticks);
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}
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return 0;
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}
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static uint32_t nxp_pit_get_pending_int(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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uint32_t mask = PIT_TFLG_TIF_MASK;
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uint32_t flags;
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int channel_id = PIT_CHANNEL_ID(dev);
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flags = PIT_GetStatusFlags(config->base, channel_id);
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return ((flags & mask) == mask);
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}
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static uint32_t nxp_pit_get_frequency(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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uint32_t clock_rate;
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if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) {
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LOG_ERR("Failed to get clock rate");
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return 0;
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}
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return clock_rate;
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}
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#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
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static void nxp_pit_isr(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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uint32_t flags;
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LOG_DBG("pit counter isr");
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for (int channel_index = 0;
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channel_index < config->num_channels;
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channel_index++) {
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flags = PIT_GetStatusFlags(config->base, channel_index);
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if (flags) {
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struct nxp_pit_channel_data *data =
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PIT_CHANNEL_DATA(config->channels[channel_index]);
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PIT_ClearStatusFlags(config->base, channel_index, flags);
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data->top_callback(dev, data->top_user_data);
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}
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}
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}
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#else
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static void nxp_pit_isr(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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struct nxp_pit_channel_data *data = PIT_CHANNEL_DATA(dev);
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pit_chnl_t channel = PIT_CHANNEL_ID(dev);
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uint32_t flags;
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LOG_DBG("pit counter isr");
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flags = PIT_GetStatusFlags(config->base, channel);
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if (flags) {
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PIT_ClearStatusFlags(config->base, channel, flags);
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if (data->top_callback) {
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data->top_callback(dev, data->top_user_data);
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}
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}
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}
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#endif /* DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) */
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static int nxp_pit_init(const struct device *dev)
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{
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const struct nxp_pit_config *config = dev->config;
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pit_config_t pit_config;
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uint32_t clock_rate;
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("Clock control device not ready");
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return -ENODEV;
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}
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PIT_GetDefaultConfig(&pit_config);
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pit_config.enableRunInDebug = config->enableRunInDebug;
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PIT_Init(config->base, &pit_config);
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clock_rate = nxp_pit_get_frequency(dev);
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#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
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config->irq_config_func(dev);
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for (int channel_index = 0;
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channel_index < config->num_channels;
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channel_index++) {
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PIT_SetTimerPeriod(config->base, channel_index,
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USEC_TO_COUNT(config->info.max_top_value, clock_rate));
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}
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#else
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for (int channel_index = 0;
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channel_index < config->num_channels;
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channel_index++) {
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if (config->irq_config_func[channel_index]) {
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config->irq_config_func[channel_index](dev);
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PIT_SetTimerPeriod(config->base, channel_index,
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USEC_TO_COUNT(config->info.max_top_value, clock_rate));
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}
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}
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#endif /* DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts) */
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return 0;
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}
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static const struct counter_driver_api nxp_pit_driver_api = {
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.start = nxp_pit_start,
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.stop = nxp_pit_stop,
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.get_value = nxp_pit_get_value,
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.set_top_value = nxp_pit_set_top_value,
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.get_pending_int = nxp_pit_get_pending_int,
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.get_top_value = nxp_pit_get_top_value,
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.get_freq = nxp_pit_get_frequency,
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};
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/* Creates a device for a channel (needed for counter API) */
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#define NXP_PIT_CHANNEL_DEV_INIT(node, pit_inst) \
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DEVICE_DT_DEFINE(node, NULL, NULL, \
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(void *) \
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&nxp_pit_##pit_inst##_channel_datas[DT_REG_ADDR(node)], \
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&nxp_pit_##pit_inst##_config, \
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POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \
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&nxp_pit_driver_api);
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/* Creates a decleration for each pit channel */
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#define NXP_PIT_CHANNEL_DECLARATIONS(node) static struct nxp_pit_channel_data \
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nxp_pit_channel_data_##node;
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/* Initializes an element of the channel data pointer array */
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#define NXP_PIT_INSERT_CHANNEL_INTO_ARRAY(node) \
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[DT_REG_ADDR(node)] = \
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&nxp_pit_channel_data_##node,
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#define NXP_PIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY(node) \
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[DT_REG_ADDR(node)] = DEVICE_DT_GET(node),
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#if DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts)
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#define NXP_PIT_IRQ_CONFIG_DECLARATIONS(n) \
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static void nxp_pit_irq_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \
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DT_INST_IRQ_BY_IDX(n, 0, priority), \
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nxp_pit_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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};
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#define NXP_PIT_SETUP_IRQ_CONFIG(n) NXP_PIT_IRQ_CONFIG_DECLARATIONS(n);
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#define NXP_PIT_SETUP_IRQ_ARRAY(ignored)
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#else
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#define NXP_PIT_IRQ_CONFIG_DECLARATIONS(n) \
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static void nxp_pit_irq_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_IRQN(n), \
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DT_IRQ(n, priority), \
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nxp_pit_isr, \
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DEVICE_DT_GET(n), 0); \
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irq_enable(DT_IRQN(n)); \
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};
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#define NXP_PIT_SETUP_IRQ_CONFIG(n) \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, NXP_PIT_IRQ_CONFIG_DECLARATIONS);
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#define NXP_PIT_INSERT_IRQ_CONFIG_INTO_ARRAY(n) \
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[DT_REG_ADDR(n)] = &nxp_pit_irq_config_func_##n,
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#define NXP_PIT_SETUP_IRQ_ARRAY(n) \
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/* Create Array of IRQs -> 1 irq func per channel */ \
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void (*nxp_pit_irq_config_array[DT_INST_FOREACH_CHILD_SEP_VARGS(n, \
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DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)]) \
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(const struct device *dev) = { \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
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NXP_PIT_INSERT_IRQ_CONFIG_INTO_ARRAY) \
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};
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#endif
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#define COUNTER_NXP_PIT_DEVICE_INIT(n) \
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\
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/* Setup the IRQ either for parent irq or per channel irq */ \
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NXP_PIT_SETUP_IRQ_CONFIG(n) \
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\
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/* Create channel declarations */ \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
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NXP_PIT_CHANNEL_DECLARATIONS) \
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\
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/* Array of channel devices */ \
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static struct nxp_pit_channel_data *const \
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nxp_pit_##n##_channel_datas \
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[DT_INST_FOREACH_CHILD_SEP_VARGS( \
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n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)] = { \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
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NXP_PIT_INSERT_CHANNEL_INTO_ARRAY) \
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}; \
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\
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/* forward declaration */ \
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static const struct nxp_pit_config nxp_pit_##n##_config; \
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\
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/* Create all the channel/counter devices */ \
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DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, \
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NXP_PIT_CHANNEL_DEV_INIT, n) \
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\
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/* This channel device array is needed by the module device ISR */ \
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const struct device *const nxp_pit_##n##_channels \
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[DT_INST_FOREACH_CHILD_SEP_VARGS( \
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n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel)] = { \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
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NXP_PIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY) \
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}; \
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\
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\
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NXP_PIT_SETUP_IRQ_ARRAY(n) \
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\
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/* This config struct is shared by all the channels and parent device */ \
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static const struct nxp_pit_config nxp_pit_##n##_config = { \
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.info = { \
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.max_top_value = \
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DT_INST_PROP(n, max_load_value), \
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.channels = 0, \
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}, \
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.base = (PIT_Type *)DT_INST_REG_ADDR(n), \
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.irq_config_func = COND_CODE_1(DT_NODE_HAS_PROP( \
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DT_COMPAT_GET_ANY_STATUS_OKAY(nxp_pit), interrupts), \
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(nxp_pit_irq_config_func_##n), \
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(&nxp_pit_irq_config_array[0])), \
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.num_channels = DT_INST_FOREACH_CHILD_SEP_VARGS( \
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n, DT_NODE_HAS_COMPAT, (+), nxp_pit_channel), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t) \
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DT_INST_CLOCKS_CELL(n, name), \
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.data = nxp_pit_##n##_channel_datas, \
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.channels = nxp_pit_##n##_channels, \
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}; \
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\
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/* Init parent device in order to handle ISR and init. */ \
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DEVICE_DT_INST_DEFINE(n, &nxp_pit_init, NULL, \
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NULL, &nxp_pit_##n##_config, POST_KERNEL, \
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CONFIG_COUNTER_INIT_PRIORITY, NULL);
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DT_INST_FOREACH_STATUS_OKAY(COUNTER_NXP_PIT_DEVICE_INIT)
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