311 lines
10 KiB
C
311 lines
10 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_counter
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#include <zephyr/drivers/counter.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/logging/log.h>
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/* ambiq-sdk includes */
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#include <am_mcu_apollo.h>
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LOG_MODULE_REGISTER(ambiq_counter, CONFIG_COUNTER_LOG_LEVEL);
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static void counter_ambiq_isr(void *arg);
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struct counter_ambiq_config {
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struct counter_config_info counter_info;
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uint32_t instance;
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uint32_t clk_src;
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void (*irq_config_func)(void);
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};
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struct counter_ambiq_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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static struct k_spinlock lock;
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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static void counter_irq_config_func(void)
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{
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/* Apollo3 counters share the same irq number, connect to counter0 once when init and handle
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* different banks in counter_ambiq_isr
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*/
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static bool global_irq_init = true;
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if (!global_irq_init) {
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return;
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}
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global_irq_init = false;
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/* Shared irq config default to ctimer0. */
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NVIC_ClearPendingIRQ(CTIMER_IRQn);
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IRQ_CONNECT(CTIMER_IRQn, DT_INST_IRQ(0, priority), counter_ambiq_isr, DEVICE_DT_INST_GET(0),
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0);
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irq_enable(CTIMER_IRQn);
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};
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#endif
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static int counter_ambiq_init(const struct device *dev)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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const struct counter_ambiq_config *cfg = dev->config;
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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/* Timer configuration */
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am_hal_ctimer_config_t sContTimer;
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/* Create 32-bit timer */
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sContTimer.ui32Link = 1;
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/* Set up TimerA. */
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sContTimer.ui32TimerAConfig = (AM_HAL_CTIMER_FN_REPEAT | AM_HAL_CTIMER_INT_ENABLE |
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(cfg->clk_src << CTIMER_CTRL0_TMRA0CLK_Pos));
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/* Set up TimerB. */
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sContTimer.ui32TimerBConfig = 0;
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am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
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am_hal_ctimer_clear(cfg->instance, AM_HAL_CTIMER_BOTH);
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am_hal_ctimer_config(cfg->instance, &sContTimer);
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counter_irq_config_func();
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#else
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am_hal_timer_config_t tc;
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am_hal_timer_default_config_set(&tc);
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tc.eInputClock = cfg->clk_src;
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tc.eFunction = AM_HAL_TIMER_FN_UPCOUNT;
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tc.ui32PatternLimit = 0;
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am_hal_timer_config(cfg->instance, &tc);
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cfg->irq_config_func();
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#endif
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_ambiq_start(const struct device *dev)
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{
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const struct counter_ambiq_config *cfg = dev->config;
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k_spinlock_key_t key = k_spin_lock(&lock);
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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am_hal_ctimer_start(cfg->instance, AM_HAL_CTIMER_TIMERA);
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#else
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am_hal_timer_start(cfg->instance);
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#endif
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_ambiq_stop(const struct device *dev)
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{
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const struct counter_ambiq_config *cfg = dev->config;
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k_spinlock_key_t key = k_spin_lock(&lock);
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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am_hal_ctimer_stop(cfg->instance, AM_HAL_CTIMER_BOTH);
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#else
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am_hal_timer_stop(cfg->instance);
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#endif
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_ambiq_get_value(const struct device *dev, uint32_t *ticks)
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{
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const struct counter_ambiq_config *cfg = dev->config;
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k_spinlock_key_t key = k_spin_lock(&lock);
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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*ticks = (am_hal_ctimer_read(cfg->instance, AM_HAL_CTIMER_TIMERA)) |
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(am_hal_ctimer_read(cfg->instance, AM_HAL_CTIMER_TIMERB) << 16);
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#else
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*ticks = am_hal_timer_read(cfg->instance);
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#endif
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_ambiq_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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ARG_UNUSED(chan_id);
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struct counter_ambiq_data *data = dev->data;
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const struct counter_ambiq_config *cfg = dev->config;
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uint32_t now;
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counter_ambiq_get_value(dev, &now);
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k_spinlock_key_t key = k_spin_lock(&lock);
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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am_hal_ctimer_int_clear(AM_HAL_CTIMER_INT_TIMERA0C0);
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am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA0C0);
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if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
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am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0,
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now + alarm_cfg->ticks);
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} else {
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am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0, alarm_cfg->ticks);
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}
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#else
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/* Enable interrupt, due to counter_ambiq_cancel_alarm() disables it*/
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am_hal_timer_interrupt_clear(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
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am_hal_timer_interrupt_enable(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
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if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
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am_hal_timer_compare1_set(cfg->instance, now + alarm_cfg->ticks);
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} else {
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am_hal_timer_compare1_set(cfg->instance, alarm_cfg->ticks);
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}
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#endif
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data->user_data = alarm_cfg->user_data;
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data->callback = alarm_cfg->callback;
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_ambiq_cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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ARG_UNUSED(chan_id);
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const struct counter_ambiq_config *cfg = dev->config;
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k_spinlock_key_t key = k_spin_lock(&lock);
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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am_hal_ctimer_int_disable(AM_HAL_CTIMER_INT_TIMERA0C0);
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/* Reset the compare register */
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am_hal_ctimer_compare_set(cfg->instance, AM_HAL_CTIMER_BOTH, 0, 0);
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#else
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am_hal_timer_interrupt_disable(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
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/* Reset the compare register */
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am_hal_timer_compare1_set(cfg->instance, 0);
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#endif
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k_spin_unlock(&lock, key);
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return 0;
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}
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static int counter_ambiq_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
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{
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const struct counter_ambiq_config *config = dev->config;
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if (cfg->ticks != config->counter_info.max_top_value) {
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return -ENOTSUP;
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} else {
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return 0;
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}
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}
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static uint32_t counter_ambiq_get_pending_int(const struct device *dev)
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{
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return 0;
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}
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static uint32_t counter_ambiq_get_top_value(const struct device *dev)
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{
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const struct counter_ambiq_config *config = dev->config;
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return config->counter_info.max_top_value;
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}
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static const struct counter_driver_api counter_api = {
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.start = counter_ambiq_start,
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.stop = counter_ambiq_stop,
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.get_value = counter_ambiq_get_value,
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.set_alarm = counter_ambiq_set_alarm,
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.cancel_alarm = counter_ambiq_cancel_alarm,
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.set_top_value = counter_ambiq_set_top_value,
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.get_pending_int = counter_ambiq_get_pending_int,
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.get_top_value = counter_ambiq_get_top_value,
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};
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#define APOLLO3_HANDLE_SHARED_TIMER_IRQ(n) \
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static const struct device *const dev_##n = DEVICE_DT_INST_GET(n); \
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struct counter_ambiq_data *const data_##n = dev_##n->data; \
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uint32_t status_##n = CTIMERn(n)->INTSTAT; \
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status_##n &= CTIMERn(n)->INTEN; \
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if (status_##n) { \
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CTIMERn(n)->INTCLR = AM_HAL_CTIMER_INT_TIMERA0C0; \
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counter_ambiq_get_value(dev_##n, &now); \
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if (data_##n->callback) { \
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data_##n->callback(dev_##n, 0, now, data_##n->user_data); \
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} \
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}
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static void counter_ambiq_isr(void *arg)
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{
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uint32_t now = 0;
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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ARG_UNUSED(arg);
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DT_INST_FOREACH_STATUS_OKAY(APOLLO3_HANDLE_SHARED_TIMER_IRQ)
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#else
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const struct device *dev = (const struct device *)arg;
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struct counter_ambiq_data *data = dev->data;
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const struct counter_ambiq_config *cfg = dev->config;
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am_hal_timer_interrupt_clear(AM_HAL_TIMER_MASK(cfg->instance, AM_HAL_TIMER_COMPARE1));
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counter_ambiq_get_value(dev, &now);
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if (data->callback) {
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data->callback(dev, 0, now, data->user_data);
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}
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#endif
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}
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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/* Apollo3 counters share the same irq number, connect irq here will cause build error, so we
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* leave this function blank here and do it in counter_irq_config_func
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*/
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#define AMBIQ_COUNTER_CONFIG_FUNC(idx) static void counter_irq_config_func_##idx(void){};
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#else
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#define AMBIQ_COUNTER_CONFIG_FUNC(idx) \
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static void counter_irq_config_func_##idx(void) \
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{ \
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NVIC_ClearPendingIRQ(DT_INST_IRQN(idx)); \
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IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), counter_ambiq_isr, \
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DEVICE_DT_INST_GET(idx), 0); \
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irq_enable(DT_INST_IRQN(idx)); \
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};
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#endif
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#define AMBIQ_COUNTER_INIT(idx) \
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static void counter_irq_config_func_##idx(void); \
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static struct counter_ambiq_data counter_data_##idx; \
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static const struct counter_ambiq_config counter_config_##idx = { \
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.instance = (DT_INST_REG_ADDR(idx) - DT_INST_REG_ADDR(0)) / DT_INST_REG_SIZE(idx), \
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.clk_src = DT_INST_PROP(idx, clk_source), \
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.counter_info = {.max_top_value = UINT32_MAX, \
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.freq = DT_INST_PROP(idx, clock_frequency), \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = 1}, \
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.irq_config_func = counter_irq_config_func_##idx, \
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}; \
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AMBIQ_COUNTER_CONFIG_FUNC(idx) \
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DEVICE_DT_INST_DEFINE(idx, counter_ambiq_init, NULL, &counter_data_##idx, \
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&counter_config_##idx, PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
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&counter_api);
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_COUNTER_INIT);
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