zephyr/boards/snps/nsim/arc_classic/support/nsim_vpx5.props

106 lines
2.7 KiB
XML

nsim_isa_family=av2hs
nsim_isa_core=4
arcver=0x54
nsim_isa_uarch_rev_major=1
nsim_isa_uarch_rev_minor=4
nsim_isa_code_density_option=2
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_unaligned_option=1
nsim_isa_div_rem_option=2
nsim_isa_swap_option=1
nsim_isa_bitscan_option=1
nsim_isa_mpy_option=9
nsim_isa_shift_option=3
nsim_isa_enable_timer_0=1
nsim_isa_timer_0_int_level=0
nsim_isa_enable_timer_1=1
nsim_isa_timer_1_int_level=0
nsim_isa_rtc_option=1
nsim_isa_num_actionpoints=8
nsim_isa_aps_feature=1
nsim_isa_stack_checking=1
nsim_isa_has_dmp_peripheral=1
nsim_isa_dmp_peripheral_version=2
nsim_isa_dmp_peripheral_count=1
nsim_isa_dmp_peripheral_base0=14
nsim_isa_dmp_peripheral_limit0=15
nsim_isa_volatile_base=12
nsim_isa_volatile_limit=0
nsim_isa_volatile_disable=0
nsim_isa_volatile_strict_ordering=1
nsim_bpu_bc_entries=1024
nsim_bpu_pt_entries=8192
nsim_bpu_rs_entries=8
nsim_bpu_bc_full_tag=1
nsim_bpu_tosq_entries=5
nsim_bpu_fb_entries=2
nsim_isa_number_of_interrupts=24
nsim_isa_number_of_levels=4
nsim_isa_number_of_external_interrupts=8
nsim_isa_intvbase_preset=0x0
nsim_isa_intvbase_ext=1
dcache=32768,64,2,a
nsim_isa_dc_version=5
nsim_isa_dc_feature_level=2
nsim_isa_dc_mem_cycles=1
icache=32768,128,4,a
nsim_isa_ic_version=4
nsim_isa_ic_feature_level=2
dccm_size=0x40000
dccm_base=0x80000000
nsim_isa_dccm_mem_cycles=1
iccm0_size=0x40000
iccm0_base=0x00000000
nsim_isa_pct_counters=16
nsim_isa_pct_interrupt=1
nsim_connect=2
nsim_connect_asi=2
nsim_connect_ici=3
nsim_connect_icd=2
nsim_connect_gfrc=4
nsim_connect_idu=2
nsim_connect_idu_cirqnum=4
nsim_connect_ivc=1
nsim_stu=4
nsim_stu_initiator_num=1
nsim_stu_initiator_dbw=128
nsim_stu_phy_ch_num=1
nsim_stu_req_fifo_depth=32
nsim_stu_buffer_size=32
nsim_stu_perf=1
nsim_isa_vec_unit=4
nsim_isa_vec_unit_rev_minor=1
nsim_isa_vec_width=512
vec_mem_size=256k
nsim_isa_vec_mem_banks=32
nsim_isa_vec_mem_bank_width=16
nsim_isa_vec_max_fetch_size=16
nsim_isa_vec_num_slots=3
nsim_isa_vec_super_with_scalar=1
nsim_isa_vec_regs=40
nsim_isa_vec_fast=0
nsim_isa_vec_num_rd_ports=6
nsim_isa_vec_num_acc=8
nsim_isa_vec_num_mpy=2
nsim_isa_vec_mpy32=1
nsim_isa_vec_num_alu=3
nsim_isa_vec_guard_bit_option=2
nsim_isa_vec_mem_topology=0
nsim_isa_vec_stack_check=1
vec_mem_base=0x90000000
nsim_cluster_version=5
nsim_isa_has_scu=1
nsim_isa_scu_stb_entries=8
nsim_isa_scu_coherent_io=1
nsim_cluster_peripheral_interfaces=1
nsim_isa_clock_gating=1
nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=23