zephyr/boards/snps/nsim/arc_classic/support/nsim_hs.props

49 lines
1.2 KiB
XML

nsim_isa_family=av2hs
nsim_isa_core=2
arcver=0x52
nsim_isa_rgf_num_banks=2
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_unaligned_option=1
nsim_isa_code_density_option=2
nsim_isa_div_rem_option=2
nsim_isa_swap_option=1
nsim_isa_bitscan_option=1
nsim_isa_mpy_option=9
nsim_isa_shift_option=3
nsim_isa_fpud_div_option=1
nsim_isa_fpu_mac_option=1
nsim_isa_enable_timer_0=1
nsim_isa_timer_0_int_level=1
nsim_isa_enable_timer_1=1
nsim_isa_timer_1_int_level=0
nsim_isa_rtc_option=1
nsim_isa_num_actionpoints=8
nsim_isa_stack_checking=1
nsim_isa_number_of_interrupts=72
nsim_isa_number_of_levels=2
nsim_isa_number_of_external_interrupts=70
nsim_isa_fast_irq=1
nsim_isa_intvbase_preset=0x0
dcache=65536,64,2,a
nsim_isa_dc_feature_level=2
nsim_isa_dc_uncached_region=1
nsim_isa_dc_mem_cycles=2
icache=65536,64,4,a
nsim_isa_ic_feature_level=2
dccm_size=0x100000
dccm_base=0x80000000
nsim_isa_dccm_mem_cycles=2
iccm0_size=0x40000
iccm0_base=0x70000000
mpu_regions=16
mpu_version=3
nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24