229 lines
5.6 KiB
Plaintext
229 lines
5.6 KiB
Plaintext
/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
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/ {
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reserved-memory {
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cpuapp_ram0x_region: memory@2f010000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f010000 DT_SIZE_K(260)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f010000 0x41000>;
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cpusec_cpuapp_ipc_shm: memory@0 {
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reg = <0x0 DT_SIZE_K(2)>;
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};
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cpuapp_cpusec_ipc_shm: memory@800 {
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reg = <0x800 DT_SIZE_K(2)>;
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};
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cpuapp_data: memory@1000 {
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reg = <0x1000 DT_SIZE_K(256)>;
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};
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};
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cpurad_ram0x_region: memory@2f051000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f051000 DT_SIZE_K(4)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f051000 0x1000>;
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cpusec_cpurad_ipc_shm: memory@0 {
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reg = <0x0 DT_SIZE_K(2)>;
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};
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cpurad_cpusec_ipc_shm: memory@800 {
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reg = <0x800 DT_SIZE_K(2)>;
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};
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};
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etr_buf_ram0x_region: memory@2f0be000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f0be000 DT_SIZE_K(4)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f0be000 0x1000>;
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/* TODO In future move this region to cpuapp_ram0x_region. */
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etr_buffer: memory@0 {
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reg = <0x0 DT_SIZE_K(4)>;
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};
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};
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cpuapp_cpurad_ram0x_region: memory@2f0bf000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f0bf000 DT_SIZE_K(4)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>,
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<NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f0bf000 0x1000>;
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cpuapp_cpurad_ipc_shm: memory@0 {
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reg = <0x0 DT_SIZE_K(2)>;
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};
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cpurad_cpuapp_ipc_shm: memory@800 {
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reg = <0x800 DT_SIZE_K(2)>;
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};
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};
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cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
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reg = <0x2f88fce0 0x80>;
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};
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cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
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reg = <0x2f88fd60 0x80>;
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};
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cpurad_cpusys_ipc_shm: memory@2f88fe00 {
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reg = <0x2f88fe00 0x80>;
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};
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cpusys_cpurad_ipc_shm: memory@2f88fe80 {
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reg = <0x2f88fe80 0x80>;
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};
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/*
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* NOTE: FLPR has a direct bridge with RAM21 that bypasses MPC.
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* This means that when this region is marked as non-executable,
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* only FLPR can execute code from it.
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*/
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ram21_region: memory@2f890000 {
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compatible = "nordic,owned-memory";
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status = "disabled";
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reg = <0x2f890000 DT_SIZE_K(64)>;
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f890000 0x10000>;
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cpuflpr_code_data: memory@0 {
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reg = <0x0 DT_SIZE_K(46)>;
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};
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cpuapp_cpuflpr_ipc_shm: memory@b800 {
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reg = <0xb800 DT_SIZE_K(1)>;
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};
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cpuflpr_cpuapp_ipc_shm: memory@bc00 {
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reg = <0xbc00 DT_SIZE_K(1)>;
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};
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dma_fast_region: memory@c000 {
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compatible = "zephyr,memory-region";
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reg = <0xc000 DT_SIZE_K(16)>;
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status = "disabled";
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#memory-region-cells = <0>;
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zephyr,memory-region = "DMA_RAM21";
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zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>;
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};
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};
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cpuppr_ram3x_region: memory@2fc00000 {
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compatible = "nordic,owned-memory";
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reg = <0x2fc00000 DT_SIZE_K(64)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWX>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2fc00000 0x10000>;
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cpuppr_code_data: memory@0 {
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reg = <0x0 DT_SIZE_K(62)>;
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};
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cpuapp_cpuppr_ipc_shm: memory@f800 {
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reg = <0xf800 DT_SIZE_K(1)>;
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};
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cpuppr_cpuapp_ipc_shm: memory@fc00 {
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reg = <0xfc00 DT_SIZE_K(1)>;
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};
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};
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cpuapp_dma_region: memory@2fc12000 {
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compatible = "nordic,owned-memory", "zephyr,memory-region";
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reg = <0x2fc12000 DT_SIZE_K(4)>;
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status = "disabled";
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#memory-region-cells = <0>;
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>;
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zephyr,memory-region = "DMA_RAM3x_APP";
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zephyr,memory-attr = <( DT_MEM_DMA )>;
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};
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cpurad_dma_region: memory@2fc13000 {
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compatible = "nordic,owned-memory", "zephyr,memory-region";
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reg = <0x2fc13000 DT_SIZE_K(1)>;
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status = "disabled";
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#memory-region-cells = <0>;
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nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
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zephyr,memory-region = "DMA_RAM3x_RAD";
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zephyr,memory-attr = <( DT_MEM_DMA )>;
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};
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};
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};
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&mram1x {
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cpurad_rx_partitions: cpurad-rx-partitions {
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compatible = "nordic,owned-partitions", "fixed-partitions";
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpurad_slot0_partition: partition@66000 {
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reg = <0x66000 DT_SIZE_K(256)>;
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};
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};
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cpuapp_rx_partitions: cpuapp-rx-partitions {
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compatible = "nordic,owned-partitions", "fixed-partitions";
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpuapp_slot0_partition: partition@a6000 {
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reg = <0xa6000 DT_SIZE_K(248)>;
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};
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cpuppr_code_partition: partition@e4000 {
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reg = <0xe4000 DT_SIZE_K(64)>;
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};
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cpuflpr_code_partition: partition@f4000 {
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reg = <0xf4000 DT_SIZE_K(48)>;
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};
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};
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cpuapp_rw_partitions: cpuapp-rw-partitions {
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compatible = "nordic,owned-partitions", "fixed-partitions";
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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dfu_partition: partition@100000 {
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reg = < 0x100000 DT_SIZE_K(908) >;
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};
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storage_partition: partition@1e3000 {
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reg = < 0x1e3000 DT_SIZE_K(24) >;
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};
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};
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};
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