405 lines
34 KiB
ReStructuredText
405 lines
34 KiB
ReStructuredText
.. zephyr:board:: max32675evkit
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Overview
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********
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The MAX32675 evaluation kit (EV kit) provides a platform for evaluation capabilities of
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the MAX32675 microcontroller, which is a highly integrated, mixed-signal, ultralow-power
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microcontroller designed for industrial and medical sensors. It contains an integrated, low-power
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HART modem which enables the bidirectional transfer of digital data over a current loop, to/from
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industrial sensors for configuration and diagnostics.
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The Zephyr port is running on the MAX32675 MCU.
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Hardware
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********
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- MAX32675 MCU:
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- Low-Power, High-Performance for IndustrialApplications
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- 100MHz Arm Cortex-M4 with FPU
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- 384KB Internal Flash
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- 160KB SRAM
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- 128kB ECC Enabled
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- 44.1μA/MHz ACTIVE Mode at 0.9V up to 12MHzCoremark®
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- 64.5μA/MHz ACTIVE Mode at 1.1V up to 100MHzCoremark
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- 2.84μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V
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- Ultra-Low-Power Analog Peripherals
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- Optimal Peripheral Mix Provides Platform Scalability
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- Two Sigma-Delta ADCs
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- 12 Channels, Assignable to Either ADC
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- Flexible Resolution and Sample Rates (24 Bits at 0.4ksps, 16 Bits at 4ksps)
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- 12-Bit DAC
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- On-Die Temperature Sensor
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- SPI (M/S)
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- Up to Two I2C
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- Up to Two UARTs
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- Up to 23 GPIOs
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- Up to Five 32-Bit Timers
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- Two Windowed Watchdog Timers
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- 8-Channel Standard DMA Controller
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- One I2S Slave for Digital Audio Interface
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- Robust Security and Reliability
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- TRNG Compliant to SP800-90B
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- Secure Nonvolatile Key Storage and AES-128/192/256
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- Secure Bootloader to Protect IP/Firmware
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- Wide, -40°C to +105°C Operating TemperatureRange
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- Benefits and Features of MAX32675EVKIT:
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- HART Compatible Secondary Master with the Ability to Connect to Existing 4-20mA Current Loop and Communicate with HART Enabled Devices
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- USB 2.0 Micro B to Serial UART
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- Two On-Board, High-Precision Voltage References
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- All GPIOs Signals Accessed Through 0.1in Headers
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- Access to 4 Analog Inputs Through SMA Connectors Configured as Differential
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- Access to 8 Analog Inputs Through 0.1in Headers Configured as Single-Ended
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- DAC Output Accessed Through SMA Connector or Test Point
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- 10-Pin SWD and Connector
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- Board Power Provided by USB Port
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- On-Board 1.0V, 1.8V, and 3.3V LDO Regulators
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- Individual Power Measurement on all IC Rails Through Jumpers
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- Two General-Purpose LEDs and Two General-Purpose Pushbutton Switches
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Supported Features
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==================
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Below interfaces are supported by Zephyr on MAX32675EVKIT.
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock and reset control |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial |
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+-----------+------------+-------------------------------------+
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| TRNG | on-chip | entropy |
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| DMA | on-chip | dma controller |
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+-----------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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+-----------+------------+-------------------------------------+
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| PWM | on-chip | pwm |
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+-----------+------------+-------------------------------------+
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| Flash | on-chip | flash |
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+-----------+------------+-------------------------------------+
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Connections and IOs
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===================
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| Name | Name | Settings | Description |
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+===========+===============+===============+==================================================================================================+
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| JP1 | P1_9 | | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects red LED D1 from P1_9. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects red LED D1 to P1_9. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP2 | P1_10 | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects green LED D2 from P1_10. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects green LED D2 to P1_10. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP3 | I2C_SCLK | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects 3V3 from I2C_SCLK. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects 3V3 to I2C0_SCLK. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP4 | I2C_SDA | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects 3V3 to I2C_SDA. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects 3V3 to I2C_SDA. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP5 | UART0_RX | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects UART0_RX (P0.8) from the SWD connector. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects UART0_RX (P0.8) to the SWD connector. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP6 | UART0_TX | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disonnects UART0_TX (P0.9) from the SWD connector. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects UART0_TX (P0.9) to the SWD connector. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP7 | REF0N | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects REF0N from ground. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects REF0N to ground. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP8 | REF1N | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects REF1N from ground. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects REF1N to ground. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP9 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_IN | | | Open | | | Disconnects TX of USB - serial bridge from HART_IN (P0.15). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_IN | | | 1-2 | | | Connects TX of USB - serial bridge to HART_IN (P0.15). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_OUT | | | Open | | | Disconnects RX of USB - serial bridge from HART_OUT (P0.14). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_OUT | | | 3-4 | | | Connects RX of USB - serial bridge to HART_OUT (P0.14). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_RTS | | | Open | | | Disconnects RTS of USB - serial bridge from HART_RTS (P1.8). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_RTS | | | 4-5 | | | Connects TX of USB - serial bridge to HART_RTS (P1.8). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_OCD | | | Open | | | Disconnects RTS of USB - serial bridge from HART_OCD (P0.16). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | HART_OCD | | | 7-8 | | | Connects TX of USB - serial bridge to HART_OCD (P0.16). | |
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| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP10 | SWD_CLK | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects boot load enable circuit from SWD_CLK (P0.1). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects boot load enable circuit to SWD_CLK (P0.1). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP11 | FSK_IN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects FSK_IN from HART analog circuitry. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects FSK_IN to HART analog circuitry. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP12 | FSK_OUT | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects FSK_OUT from HART analog circuitry. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects FSK_OUT to HART analog circuitry. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP13 | RCV_FSK | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects RCV_FSK from CC LOOP. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects RCV_FSK to CC LOOP. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP14 | RCV_FSK | +-----------+ | +--------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects RCV_FSK from XFMR LOOP. | |
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| | | +-----------+ | +--------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects RCV_FSK to XFMR LOOP. | |
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| | | +-----------+ | +--------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP15 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects 249Ω resistor shunt from CC LOOP. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects 249Ω resistor shunt to CC LOOP. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP16 | N/A | N/A | N/A |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP17 | N/A | N/A | N/A |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP18 | N/A | N/A | N/A |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP19 | HART_RTS | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Enables HART_RTS optical transceiver. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Bypasses HART_RTS optical transceiver. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP20 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects 249Ω resistor shunt from XFMR LOOP. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects 249Ω resistor shunt to XFMR LOOP. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP21 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects power from VDDIO. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects power to VDDIO. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP22 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects power from VDDA. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects power to VDDA. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP23 | VDD18 | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects power from VDD18. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects power to VDD18. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP24 | VCORE | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects power from VCORE. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Closed | | | Connects power to VCORE. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP25 | REF0P | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Connects OB_VREF to REF0P. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | Connects INT_VREF to REF0P. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP26 | REF1P | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Connects OB_VREF to REF1P. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | Connects INT_VREF to REF1P. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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Detailed Description of Hardware
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================================
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HART Interface
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**************
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The HART circuitry acts as a secondary master with the ability to connect to an existing 4mA–20mA
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current loop and communicates with HART-enabled devices. Connection to a capacitance coupled loop
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through JH8 and a transformer loop is through JH9. HART communication to the MAX32675 is through
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the USB connector CN1.
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USB-to-HART Interface
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*********************
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The EV kit provides a USB-to-HART bridge chip, FTDI FT231. This bridge eliminates the requirement
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for a physical RS-232 COM port. Instead, the IC’s HART access is through the Micro-USB type-B
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connector, CN1. Virtual COM port drivers and guides for installing Windows® drivers are available
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at the FTDI chip website.
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Power Supply
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************
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The EV kit is powered by +5V that is made available through VBUS on the Micro-USB type-B
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connector CN1. A blue LED (D5) illuminates when the board is powered. Green LEDs (D6), (D7),
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and (D8) illuminate when the 3V3, 1V8, and 1V0 LDOs are powered, respectively.
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Current Monitoring
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******************
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Two pin headers provide convenient current monitoring points for VDDIO EN (JP21),
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VDDA EN (JP22), VDD18 EN (JP23), and VCORE (JP24).
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To accurately achieve the low-power current values, the EVkit needs to be configured
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such that no outside influence (i.e., pullups, external clock, debugger connector, etc.)
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causes a current source or sink on that GPIO.
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Clocking
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********
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The MAX32675 clocking is provided by an external 16MHz crystal (Y1).
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Voltage Reference
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*****************
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The differential reference inputs REF0 and REF1 can be sourced by an internal reference (INT_VREF)
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or a higher precision external reference source, MAX6071.
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This is selected by jumpers JP25 and JP26.
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UART Interface
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**************
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The EV kit provides a USB-to-UART bridge chip (the FTDI FT230XS-R). This bridge eliminates
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the requirement for a physical RS-232 COM port. Instead, the IC’s UART access is through
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the Micro USB type-B connector (CN1). The USB-to-UART bridge can be connected to the IC’s UART0
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or LPUART0 with jumpers JP10 (RX0) and JP11 (TX0). Virtual COM port drivers and guides for
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installing Windows® drivers are available on the FTDI Chip website.
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Boot Loader
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***********
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Boot load is activated by boot load enable slide switch SW5.
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GPIO and Alternate Function Headers
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***********************************
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GPIO and alternate function signals from the MAX32675 can be accessed through 0.1in
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spaced headers JH1, JH2, JH3, and JH4.
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Analog Input Access
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*******************
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Analog inputs (AIN0–AIN3) can be accessed differentially from SMA connectors J2 and J3 or
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separately from TP10, TP12, TP15, and TP16, respectively. Analog inputs (AIN4–AIN11) can be
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accessed through 0.1in spaced headers JH5 and JH6.
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I2C Pullups
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***********
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The I2C port can independently pulled up to 3V3 through JP3 (I2C_SCL) and JP4 (I2C_SDA).
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Reset Pushbutton
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****************
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The IC can be reset by pushbutton SW3.
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Indicator LEDs
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**************
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General-purpose indicators LED D1 (red) is connected to GPIO P1.9 and LED D2 (green) is connected
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to GPIO P1.10.
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GPIO Pushbutton Switches
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************************
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The two general-purpose pushbuttons (SW1 and SW2) are connected to GPIO P1.11 and P1.12,
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respectively. If the pushbutton is pressed, the attached port pin is pulled low.
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Programming and Debugging
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*************************
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Flashing
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========
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SWD debug can be accessed through an Arm Cortex 10-pin connector (J5).
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Logic levels are set to 3V3 by default, but they can be set to 1.8V if TP5 (VDD_VDDA_EXT)
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is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect
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the 3.3V LDO if supplying VDD and VDDA externally.
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Once the debug probe is connected to your host computer, then you can simply run the
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``west flash`` command to write a firmware image into flash.
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.. note::
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This board uses OpenOCD as the default debug interface. You can also use
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a Segger J-Link with Segger's native tooling by overriding the runner,
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appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
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be connected to the standard 2*5 pin debug connector (JH2) using an
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appropriate adapter board and cable.
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Debugging
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=========
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Please refer to the `Flashing`_ section and run the ``west debug`` command
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instead of ``west flash``.
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References
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**********
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- `MAX32675EVKIT web page`_
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.. _MAX32675EVKIT web page:
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https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32675evkit.html
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