329 lines
7.1 KiB
Plaintext
329 lines
7.1 KiB
Plaintext
/*
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* Copyright (c) 2024 BayLibre
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/l4/stm32l4s5Xi.dtsi>
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#include <st/l4/stm32l4s5qiix-pinctrl.dtsi>
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#include "arduino_r3_connector.dtsi"
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#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
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/ {
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model = "Analog Devices Inc. EVAL-ADIN1110EBZ board";
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compatible = "adi,eval-adin1110ebz";
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chosen {
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zephyr,console = &usart1;
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zephyr,shell-uart = &usart1;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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zephyr,flash-controller = &mx25r6435f;
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};
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ram0: psram@60000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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device_type = "memory";
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reg = <0x60000000 DT_SIZE_M(8)>;
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zephyr,memory-region = "RAM0";
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};
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leds { /* Respecting pcb silkscreen naming */
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compatible = "gpio-leds";
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green_led: led_uC0 {
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gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
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label = "Status uC0";
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};
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red_led: led_uC1 {
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gpios = <&gpioe 2 GPIO_ACTIVE_LOW>;
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label = "Status uC1 ";
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};
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yellow_led: led_uC2 {
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gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
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label = "Status uC2";
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};
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blue_led: led_uC3 {
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gpios = <&gpiog 15 GPIO_ACTIVE_LOW>;
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label = "Status uC3";
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};
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};
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aliases {
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led0 = &green_led;
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watchdog0 = &iwdg;
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ambient-temp0 = &adt7420;
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};
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soc {
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fmc: memory-controller@a0000000 {
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compatible = "st,stm32-fmc";
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reg = <0xa0000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
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sram {
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compatible = "st,stm32-fmc-nor-psram";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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};
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&clk_lsi {
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status = "okay";
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};
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&clk_hsi48 {
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status = "okay";
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};
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&clk_hsi {
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status = "okay";
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};
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&pll {
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div-m = <4>;
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mul-n = <40>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(80)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x00000000 DT_SIZE_K(64)>;
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read-only;
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};
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/*
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* The flash starting at offset 0x10000 and ending at
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* offset 0x1ffff is reserved for use by the application.
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*/
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slot0_partition: partition@20000 {
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label = "image-0";
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reg = <0x00020000 DT_SIZE_K(432)>;
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};
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slot1_partition: partition@8c000 {
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label = "image-1";
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reg = <0x0008C000 DT_SIZE_K(432)>;
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};
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scratch_partition: partition@f8000 {
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label = "image-scratch";
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reg = <0x000F8000 DT_SIZE_K(16)>;
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};
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storage_partition: partition@fc000 {
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label = "storage";
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reg = <0x000fc000 DT_SIZE_K(16)>;
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};
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};
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};
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&iwdg {
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status = "okay";
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};
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&rng {
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status = "okay";
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};
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&dma1 {
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status = "okay";
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};
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&dmamux1 {
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status = "okay";
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};
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&usart1 { /* USB FT232 */
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-names = "default";
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current-speed = <115200>;
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status = "okay";
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};
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&uart4 { /* ARDUINO P405 1 & 2 */
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pinctrl-0 = <&uart4_tx_pa0 &uart4_rx_pa1>;
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pinctrl-names = "default";
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current-speed = <115200>;
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_scl_pg14 &i2c1_sda_pg13>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <I2C_BITRATE_FAST>;
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};
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&i2c3 {
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pinctrl-0 = <&i2c3_scl_pg7 &i2c3_sda_pg8>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <I2C_BITRATE_FAST>;
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adt7420: adt7420@48 {
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compatible = "adi,adt7420";
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reg = <0x48>;
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};
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};
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&spi1 {
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pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
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pinctrl-names = "default";
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cs-gpios = <&gpioa 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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};
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&spi2 {
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pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
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pinctrl-names = "default";
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cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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dmas = <&dmamux1 2 13 (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC |
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STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>,
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<&dmamux1 3 12 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC |
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STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>;
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dma-names = "tx", "rx";
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status = "okay";
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adin1110: adin1110@0 {
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compatible = "adi,adin1110";
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reg = <0x0>;
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spi-max-frequency = <25000000>;
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int-gpios = <&gpiob 11 GPIO_ACTIVE_LOW>;
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reset-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
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status = "okay";
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spi-oa;
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spi-oa-protection;
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port1 {
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local-mac-address = [ 00 E0 22 FE DA C8 ];
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};
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mdio {
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compatible = "adi,adin2111-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <0x1>;
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compatible = "adi,adin2111-phy";
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};
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};
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};
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};
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&spi3 {
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pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>;
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pinctrl-names = "default";
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status = "okay";
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};
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&timers2 {
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status = "okay";
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pwm2: pwm {
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status = "okay";
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pinctrl-0 = <&tim2_ch1_pa15>;
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pinctrl-names = "default";
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};
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};
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&rtc {
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
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<&rcc STM32_SRC_LSI RTC_SEL(2)>;
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status = "okay";
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};
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zephyr_udc0: &usbotg_fs {
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pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12
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&usb_otg_fs_id_pa10>;
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pinctrl-names = "default";
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status = "okay";
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};
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&octospi1 {
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pinctrl-0 = <&octospim_p1_clk_pa3 &octospim_p1_ncs_pa4
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&octospim_p1_io0_pb1 &octospim_p1_io1_pb0
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&octospim_p1_io2_pa7 &octospim_p1_io3_pa6>;
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pinctrl-names = "default";
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dmas = <&dma1 0 40 0x480>; /* request 40 for OCTOSPI1 */
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dma-names = "tx_rx";
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status = "okay";
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mx25r6435f: ospi-nor-flash@90000000 {
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compatible = "st,stm32-ospi-nor";
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reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Megabits */
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ospi-max-frequency = <DT_FREQ_M(26)>; /* for Voltage Range 2 */
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spi-bus-width = <OSPI_QUAD_MODE>;
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data-rate = <OSPI_STR_TRANSFER>;
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writeoc="PP_1_4_4";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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store_partition: partition@0 {
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label = "store";
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reg = <0x00000000 DT_SIZE_M(8)>;
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};
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};
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};
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};
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&fmc {
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pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
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&fmc_nce_pd7 &fmc_nwe_pd5 &fmc_noe_pd4
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&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3
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&fmc_a4_pf4 &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13
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&fmc_a8_pf14 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
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&fmc_a12_pg2 &fmc_a13_pg3 &fmc_a14_pg4 &fmc_a15_pg5
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&fmc_a16_pd11 &fmc_a17_pd12 &fmc_a18_pd13 &fmc_a19_pe3
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&fmc_a20_pe4 &fmc_a21_pe5
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&fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
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&fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
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&fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
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&fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>;
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pinctrl-names = "default";
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sram {
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bank@0 {
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reg = <0x0>;
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st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
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STM32_FMC_MEMORY_TYPE_SRAM
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STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
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STM32_FMC_BURST_ACCESS_MODE_DISABLE
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STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
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STM32_FMC_WAIT_TIMING_BEFORE_WS
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STM32_FMC_WRITE_OPERATION_ENABLE
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STM32_FMC_WAIT_SIGNAL_DISABLE
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STM32_FMC_EXTENDED_MODE_DISABLE
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STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
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STM32_FMC_WRITE_BURST_DISABLE
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STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
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STM32_FMC_WRITE_FIFO_DISABLE
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STM32_FMC_PAGE_SIZE_NONE>;
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st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
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};
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};
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};
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