/*
 * Copyright (c) 2018 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <st/f1/stm32f1.dtsi>

/ {
	sram0: memory@20000000 {
		reg = <0x20000000 DT_SIZE_K(20)>;
	};

	soc {
		compatible = "st,stm32f103", "st,stm32f1", "simple-bus";

		flash-controller@40022000 {
			flash0: flash@8000000 {
				reg = <0x08000000 DT_SIZE_K(64)>;
				erase-block-size = <DT_SIZE_K(1)>;
			};
		};

		/* spi2 is present on all STM32F103x8 SoCs except
		 * STM32F103T8. Delete node in stm32f103t8.dtsi.
		 */
		spi2: spi@40003800 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
			interrupts = <36 5>;
			status = "disabled";
		};

		usb: usb@40005c00 {
			compatible = "st,stm32-usb";
			reg = <0x40005c00 0x400>;
			interrupts = <20 0>;
			interrupt-names = "usb";
			num-bidir-endpoints = <8>;
			ram-size = <512>;
			status = "disabled";
			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
			phys = <&usb_fs_phy>;
		};

		can1: can@40006400 {
			compatible = "st,stm32-bxcan";
			reg = <0x40006400 0x400>;
			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
			interrupt-names = "TX", "RX0", "RX1", "SCE";
			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
			status = "disabled";
		};
	};

	usb_fs_phy: usbphy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};