/*
 * Copyright (c) 2019 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <mem.h>
#include <freq.h>
#include <xtensa/xtensa.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/clock/esp32_clock.h>
#include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
#include <dt-bindings/pinctrl/esp32-pinctrl.h>
#include <zephyr/dt-bindings/pwm/pwm.h>

/ {
	chosen {
		zephyr,canbus = &twai;
		zephyr,entropy = &trng0;
		zephyr,flash-controller = &flash;
		zephyr,bt-hci = &esp32_bt_hci;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "espressif,xtensa-lx6";
			reg = <0>;
			cpu-power-states = <&light_sleep &deep_sleep>;
			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
			clock-frequency = <DT_FREQ_M(240)>;
			xtal-freq = <DT_FREQ_M(40)>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "espressif,xtensa-lx6";
			reg = <1>;
			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
			clock-frequency = <DT_FREQ_M(240)>;
			xtal-freq = <DT_FREQ_M(40)>;
		};

		power-states {
			light_sleep: light_sleep {
				compatible = "zephyr,power-state";
				power-state-name = "standby";
				min-residency-us = <200>;
				exit-latency-us = <60>;
			};

			deep_sleep: deep_sleep {
				compatible = "zephyr,power-state";
				power-state-name = "soft-off";
				min-residency-us = <2000>;
				exit-latency-us = <212>;
			};
		};
	};

	wifi: wifi {
		compatible = "espressif,esp32-wifi";
		status = "disabled";
	};

	esp32_bt_hci: esp32_bt_hci {
		compatible = "espressif,esp32-bt-hci";
		status = "disabled";
	};

	eth: eth {
		compatible = "espressif,esp32-eth";
		interrupts = <ETH_MAC_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
		interrupt-parent = <&intc>;
		clocks = <&rtc ESP32_EMAC_MODULE>;
		status = "disabled";
	};

	mdio: mdio {
		compatible = "espressif,esp32-mdio";
		clocks = <&rtc ESP32_EMAC_MODULE>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	pinctrl: pin-controller {
		compatible = "espressif,esp32-pinctrl";
		status = "okay";
	};

	soc {
		sram0: memory@3ffb0000 {
			compatible = "mmio-sram";
			reg = <0x3FFB0000 0x2c200>;
		};

		ipmmem0: memory@3ffe5230 {
			compatible = "mmio-sram";
			reg = <0x3FFE5230 0x400>;
		};

		shm0: memory@3ffe5630 {
			compatible = "mmio-sram";
			reg = <0x3FFE5630 0x3C00>;
		};

		intc: interrupt-controller@3ff00104 {
			#interrupt-cells = <3>;
			compatible = "espressif,esp32-intc";
			interrupt-controller;
			reg = <0x3ff00104 0x114>;
			status = "okay";
		};

		rtc: rtc@3ff48000 {
			compatible = "espressif,esp32-rtc";
			reg = <0x3ff48000 0x0D8>;
			fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
			slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
			#clock-cells = <1>;
			status = "okay";

		};

		rtc_timer: rtc_timer@3ff48004 {
			reg = <0x3ff48004 0xC>;
			compatible = "espressif,esp32-rtc-timer";
			clocks = <&rtc ESP32_MODULE_MAX>;
			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			status = "okay";
		};

		flash: flash-controller@3ff42000 {
			compatible = "espressif,esp32-flash-controller";
			reg = <0x3ff42000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@0 {
				compatible = "soc-nv-flash";
				erase-block-size = <4096>;
				write-block-size = <4>;
				/* Flash size is specified in SOC/SIP dtsi */
			};
		};

		psram0: psram@3f800000 {
			device_type = "memory";
			compatible = "mmio-sram";
			/* PSRAM size is specified in SOC/SIP dtsi */
			reg = <0x3f800000 DT_SIZE_M(2)>;
			status = "disabled";
		};

		ipm0: ipm@3ffed238 {
			compatible = "espressif,esp32-ipm";
			reg = <0x3FFED238 0x8>;
			status = "disabled";
			shared-memory = <&ipmmem0>;
			shared-memory-size = <0x400>;
			interrupts =
				<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
				<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
		};

		mbox0: mbox@3ffed240 {
			compatible = "espressif,mbox-esp32";
			reg = <0x3FFED240 0x8>;
			status = "disabled";
			shared-memory = <&ipmmem0>;
			shared-memory-size = <0x400>;
			interrupts =
				<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
				<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			#mbox-cells = <1>;
		};

		ipi0: ipi@3f4c0058 {
			compatible = "espressif,crosscore-interrupt";
			reg = <0x3f4c0058 0x4>;
			interrupts = <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
		};

		ipi1: ipi@3f4c005c {
			compatible = "espressif,crosscore-interrupt";
			reg = <0x3f4c005c 0x4>;
			interrupts = <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
		};

		uart0: uart@3ff40000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff40000 0x400>;
			interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_UART0_MODULE>;
			status = "disabled";
		};

		uart1: uart@3ff50000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff50000 0x400>;
			interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_UART1_MODULE>;
			status = "disabled";
		};

		uart2: uart@3ff6e000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff6E000 0x400>;
			interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_UART2_MODULE>;
			status = "disabled";
		};

		pcnt: pcnt@3ff57000 {
			compatible = "espressif,esp32-pcnt";
			reg = <0x3ff57000 0x1000>;
			interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_PCNT_MODULE>;
			status = "disabled";
		};

		ledc0: ledc@3ff59000 {
			compatible = "espressif,esp32-ledc";
			#pwm-cells = <3>;
			reg = <0x3ff59000 0x800>;
			clocks = <&rtc ESP32_LEDC_MODULE>;
			status = "disabled";
		};

		mcpwm0: mcpwm@3ff5e000 {
			compatible = "espressif,esp32-mcpwm";
			reg = <0x3ff5e000 0x1000>;
			interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_PWM0_MODULE>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		mcpwm1: mcpwm@3ff6c000 {
			compatible = "espressif,esp32-mcpwm";
			reg = <0x3ff6c000 0x1000>;
			interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_PWM1_MODULE>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		gpio: gpio {
			compatible = "simple-bus";
			gpio-map-mask = <0xffffffe0 0xffffffc0>;
			gpio-map-pass-thru = <0x1f 0x3f>;
			gpio-map = <
				0x00 0x0 &gpio0 0x0 0x0
				0x20 0x0 &gpio1 0x0 0x0
			>;
			#gpio-cells = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gpio0: gpio@3ff44000 {
				compatible = "espressif,esp32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x3ff44000 0x800>;
				interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
				interrupt-parent = <&intc>;
				/* Maximum available pins (per port)
				 * Actual occupied pins are specified
				 * on part number dtsi level, using
				 * the `gpio-reserved-ranges` property.
				 */
				ngpios = <32>;   /* 0..31 */
			};

			gpio1: gpio@3ff44800 {
				compatible = "espressif,esp32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x3ff44800 0x800>;
				interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
				interrupt-parent = <&intc>;
				ngpios = <8>;   /* 32..39 */
			};
		};

		touch: touch@3ff48858 {
			compatible = "espressif,esp32-touch";
			reg = <0x3ff48858 0x38>;
			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		i2c0: i2c@3ff53000 {
			compatible = "espressif,esp32-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3ff53000 0x1000>;
			interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_I2C0_MODULE>;
			status = "disabled";
		};

		i2c1: i2c@3ff67000 {
			compatible = "espressif,esp32-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3ff67000 0x1000>;
			interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_I2C1_MODULE>;
			status = "disabled";
		};

		trng0: trng@3ff75144 {
			compatible = "espressif,esp32-trng";
			reg = <0x3FF75144 0x4>;
			status = "disabled";
		};

		wdt0: watchdog@3ff5f048 {
			compatible = "espressif,esp32-watchdog";
			reg = <0x3ff5f048 0x20>;
			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_TIMG0_MODULE>;
			status = "okay";
		};

		wdt1: watchdog@3ff60048 {
			compatible = "espressif,esp32-watchdog";
			reg = <0x3ff60048 0x20>;
			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_TIMG1_MODULE>;
			status = "disabled";
		};

		spi2: spi@3ff64000 {
			compatible = "espressif,esp32-spi";
			reg = <0x3ff64000 DT_SIZE_K(4)>;
			interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_HSPI_MODULE>;
			dma-clk = <ESP32_SPI_DMA_MODULE>;
			dma-host = <0>;
			status = "disabled";
		};

		spi3: spi@3ff65000 {
			compatible = "espressif,esp32-spi";
			reg = <0x3ff65000 DT_SIZE_K(4)>;
			interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_VSPI_MODULE>;
			dma-clk = <ESP32_SPI_DMA_MODULE>;
			dma-host = <1>;
			status = "disabled";
		};

		twai: can@3ff6b000 {
			compatible = "espressif,esp32-twai";
			reg = <0x3ff6b000 DT_SIZE_K(4)>;
			interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_TWAI_MODULE>;
			status = "disabled";
		};

		timer0: counter@3ff5f000 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff5f000 DT_SIZE_K(4)>;
			group = <0>;
			index = <0>;
			interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		timer1: counter@3ff5f024 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff5f024 DT_SIZE_K(4)>;
			group = <0>;
			index = <1>;
			interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		timer2: counter@3ff60000 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff60000 DT_SIZE_K(4)>;
			group = <1>;
			index = <0>;
			interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		timer3: counter@3ff60024 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff60024 DT_SIZE_K(4)>;
			group = <1>;
			index = <1>;
			interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		dac: dac@3ff48800 {
			compatible = "espressif,esp32-dac";
			reg = <0x3ff48800 0x100>;
			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_SARADC_MODULE>;
			#io-channel-cells = <1>;
			status = "disabled";
		};

		adc0: adc@3ff48800 {
			compatible = "espressif,esp32-adc";
			reg = <0x3ff48800 10>;
			unit = <1>;
			channel-count = <8>;
			#io-channel-cells = <1>;
			status = "disabled";
		};

		adc1: adc@3ff48890 {
			compatible = "espressif,esp32-adc";
			reg = <0x3ff48890 10>;
			unit = <2>;
			channel-count = <10>;
			#io-channel-cells = <1>;
			status = "disabled";
		};

		sdhc: sdhc@3ff68000 {
			compatible = "espressif,esp32-sdhc";
			reg = <0x3ff68000 0x1000>;
			interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_SDMMC_MODULE>;
			#address-cells = <1>;
			#size-cells = <0>;

			sdhc0: sdhc@0 {
				compatible = "espressif,esp32-sdhc-slot";
				reg = <0>;
				status = "disabled";
			};

			sdhc1: sdhc@1 {
				compatible = "espressif,esp32-sdhc-slot";
				reg = <1>;
				status = "disabled";
			};
		};
	};
};