/* * Copyright (c) 2023 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ #include "skeleton.dtsi" #include #include #include / { power-states { d0i0: d0i0 { compatible = "zephyr,power-state"; power-state-name = "runtime-idle"; min-residency-us = <500>; substate-id = <1>; }; d0i2: d0i2 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-ram"; min-residency-us = <10000>; substate-id = <3>; }; d0i3: d0i3 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-disk"; min-residency-us = <3000000>; substate-id = <4>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu0@0 { device_type = "cpu"; compatible = "intel,ish"; reg = <0>; cpu-power-states = <&d0i0 &d0i2 &d0i3>; }; }; intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; reg = <0xfec00000 0x1000>; interrupt-controller; }; intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; #interrupt-cells = <3>; #address-cells = <1>; }; sram: memory@ff200000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0xff200000 DT_SIZE_K(640)>; }; aon: memory@ff800000 { device_type = "memory"; compatible = "zephyr,memory-region", "mmio-sram"; reg = <0xff800000 DT_SIZE_K(8)>; zephyr,memory-region = "AON"; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; hpet: hpet@4700000{ compatible = "intel,hpet"; reg = <0x04700000 0x400>; interrupt-parent = <&intc>; interrupts = <14 IRQ_TYPE_FIXED_LEVEL_HIGH 2>; status = "okay"; }; ipmhost: ipm@4100000 { compatible = "intel,sedi-ipm"; reg = <0x4100000 0x1000>; peripheral-id = <0>; interrupt-parent = <&intc>; interrupts = <0 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; status = "okay"; }; uart0: uart@8100000 { compatible = "intel,sedi-uart"; reg = <0x08100000 0x1000>; interrupt-parent = <&intc>; interrupts = <23 IRQ_TYPE_LOWEST_EDGE_RISING 6>; peripheral-id = <0>; current-speed = <115200>; status = "okay"; }; i2c0: i2c@0 { compatible = "intel,sedi-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1000>; peripheral-id = <0>; interrupt-parent = <&intc>; interrupts = <15 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; clock-frequency = ; status = "okay"; }; i2c1: i2c@2000 { compatible = "intel,sedi-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x00002000 0x1000>; peripheral-id = <1>; interrupt-parent = <&intc>; interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; clock-frequency = ; status = "okay"; }; i2c2: i2c@4000 { compatible = "intel,sedi-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x00004000 0x1000>; peripheral-id = <2>; interrupt-parent = <&intc>; interrupts = <17 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; clock-frequency = ; status = "disabled"; }; gpio0: gpio@100000 { compatible = "intel,sedi-gpio"; gpio-controller; #gpio-cells = <2>; peripheral-id = <0>; reg = <0x00100000 0x1000>; interrupt-parent = <&intc>; ngpios = <32>; interrupts = <13 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; status = "okay"; }; spi0: spi@8000000 { compatible = "intel,sedi-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x8000000 0x1000>; peripheral-id = <0>; interrupt-parent = <&intc>; interrupts = <19 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; status = "okay"; }; spi1: spi@8002000 { compatible = "intel,sedi-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x8002000 0x1000>; peripheral-id = <1>; interrupt-parent = <&intc>; interrupts = <20 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; status = "disabled"; }; dma0: dma@10100000 { compatible = "intel,sedi-dma"; #dma-cells = <2>; dma-channels = <8>; peripheral-id = <0>; reg = <0x10100000 0x1000>; interrupts = <11 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>; interrupt-parent = <&intc>; dma-buf-size-alignment = <4>; dma-copy-alignment = <4>; status = "okay"; }; }; };