/*
 * Copyright (c) 2018 Intel Corporation Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* SoC level DTS fixup file */

#define CONFIG_PHYS_RAM_ADDR                    CONFIG_SRAM_BASE_ADDRESS

#define CONFIG_PHYS_LOAD_ADDR                   CONFIG_FLASH_BASE_ADDRESS

#define CONFIG_RAM_SIZE                         CONFIG_SRAM_SIZE

#define CONFIG_ROM_SIZE                         CONFIG_FLASH_SIZE

#define CONFIG_IOAPIC_BASE_ADDRESS              INTEL_IOAPIC_FEC00000_BASE_ADDRESS

/* End of SoC Level DTS fixup file */