#include #include / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-m4f"; reg = <0>; }; }; flash0: flash@0 { compatible = "soc-nv-flash"; label = "FLASH_0"; }; sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; soc { uart0: uart@40010000 { /* USART0 */ compatible = "silabs,efm32-usart"; reg = <0x40010000 0x400>; interrupts = <11 0 12 0>; status = "disabled"; label = "UART_0"; }; uart1: uart@40010400 { /* USART1 */ compatible = "silabs,efm32-usart"; reg = <0x40010400 0x400>; interrupts = <19 0 20 0>; status = "disabled"; label = "UART_1"; }; gpio@4000a400 { compatible = "silabs,efr32xg1-gpio"; reg = <0x4000a400 0xc00>; interrupts = <9 2 17 2>; interrupt-names = "GPIO_EVEN", "GPIO_ODD"; label = "GPIO"; ranges; #address-cells = <1>; #size-cells = <1>; gpioa: gpio@4000a000 { compatible = "silabs,efr32xg1-gpio-port"; reg = <0x4000a000 0x30>; label = "GPIO_A"; gpio-controller; #gpio-cells = <2>; }; gpiob: gpio@4000a030 { compatible = "silabs,efr32xg1-gpio-port"; reg = <0x4000a030 0x30>; label = "GPIO_B"; gpio-controller; #gpio-cells = <2>; }; gpioc: gpio@4000a060 { compatible = "silabs,efr32xg1-gpio-port"; reg = <0x4000a060 0x30>; label = "GPIO_C"; gpio-controller; #gpio-cells = <2>; }; gpiod: gpio@4000a090 { compatible = "silabs,efr32xg1-gpio-port"; reg = <0x4000a090 0x30>; label = "GPIO_D"; gpio-controller; #gpio-cells = <2>; }; gpioe: gpio@4000a0c0 { compatible = "silabs,efr32xg1-gpio-port"; reg = <0x4000a0c0 0x30>; label = "GPIO_E"; gpio-controller; #gpio-cells = <2>; }; gpiof: gpio@4000a0f0 { compatible = "silabs,efr32xg1-gpio-port"; reg = <0x4000af0 0x30>; label = "GPIO_F"; gpio-controller; #gpio-cells = <2>; }; }; }; }; &nvic { arm,num-irq-priority-bits = <3>; };