/* * SPDX-License-Identifier: Apache-2.0 * * Copyright (C) 2023, Intel Corporation * */ #include #include #include #include / { cpus { #address-cells = <1>; #size-cells= <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x0>; }; cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x100>; }; cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a76"; enable-method = "psci"; reg = <0x200>; }; cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a76"; enable-method = "psci"; reg = <0x300>; }; }; gic: interrupt-controller@1d000000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0x1d000000 0x10000>, /* GICD */ <0x1d060000 0x80000>; /* GICR */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; #address-cells = <1>; #size-cells = <1>; its: msi-controller@1d040000 { compatible = "arm,gic-v3-its"; reg = <0x1d040000 0x20000>; status = "disabled"; }; }; arch_timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , , , ; }; sysmgr: sysmgr@10d12000 { compatible = "syscon"; reg = <0x10d12000 0x1000>; }; clock: clock@10d10000 { compatible = "intel,agilex5-clock"; reg = <0x10d10000 0x1000>; #clock-cells = <1>; }; psci { compatible = "arm,psci-1.1"; method = "smc"; }; /* This is for setting the MMU region for pinmux */ pinmux: pinmux@10d13000 { compatible = "syscon"; reg = <0x10d13000 0x1000>; }; mem0: memory@80100000 { device_type = "memory"; reg = <0x80100000 DT_SIZE_M(8)>; }; uart0: uart@10c02000 { compatible = "ns16550"; reg-shift = <2>; reg = <0x10c02000 0x100>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "irq_0"; clock-frequency = <100000000>; resets = <&reset RSTMGR_UART0_RSTLINE>; status = "disabled"; }; reset: reset-controller@10D11000 { compatible = "intel,socfpga-reset"; reg = <0x10D11000 0x100>; active-low; #reset-cells = <1>; status = "okay"; }; };