/*
 * Copyright (c) 2019 Argentum Systems Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/f1/stm32f1.dtsi>

/ {
	clocks {
		/delete-node/ pll;

		pll: pll {
			#clock-cells = <0>;
			compatible = "st,stm32f105-pll-clock";
			status = "disabled";
		};

		pll2: pll2 {
			#clock-cells = <0>;
			compatible = "st,stm32f105-pll2-clock";
			clocks = <&clk_hse>;
			status = "disabled";
		};
	};

	soc {
		compatible = "st,stm32f105", "st,stm32f1", "simple-bus";

		flash-controller@40022000 {
			flash0: flash@8000000 {
				erase-block-size = <DT_SIZE_K(2)>;
			};
		};

		can1: can@40006400 {
			compatible = "st,stm32-bxcan";
			reg = <0x40006400 0x400>;
			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
			interrupt-names = "TX", "RX0", "RX1", "SCE";
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
			status = "disabled";
		};

		can2: can@40006800 {
			compatible = "st,stm32-bxcan";
			reg = <0x40006800 0x400>;
			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
			interrupt-names = "TX", "RX0", "RX1", "SCE";
			/* also enabling clock for can1 (master instance) */
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
			status = "disabled";
		};

		dac1: dac@40007400 {
			compatible = "st,stm32-dac";
			reg = <0x40007400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		uart4: serial@40004c00 {
			compatible = "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
			resets = <&rctl STM32_RESET(APB1, 19U)>;
			interrupts = <52 0>;
			status = "disabled";
		};

		uart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
			resets = <&rctl STM32_RESET(APB1, 20U)>;
			interrupts = <53 0>;
			status = "disabled";
		};

		spi2: spi@40003800 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
			interrupts = <36 5>;
			status = "disabled";
		};

		spi3: spi@40003c00 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
			interrupts = <51 5>;
			status = "disabled";
		};

		timers5: timers@40000c00 {
			compatible = "st,stm32-timers";
			reg = <0x40000c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
			resets = <&rctl STM32_RESET(APB1, 3U)>;
			interrupts = <50 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers6: timers@40001000 {
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
			resets = <&rctl STM32_RESET(APB1, 4U)>;
			interrupts = <54 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";
		};

		timers7: timers@40001400 {
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
			resets = <&rctl STM32_RESET(APB1, 5U)>;
			interrupts = <55 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";
		};

		usbotg_fs: usb@50000000 {
			compatible = "st,stm32-otgfs";
			reg = <0x50000000 0x40000>;
			interrupts = <67 0>;
			interrupt-names = "otgfs";
			num-bidir-endpoints = <4>;
			ram-size = <1280>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00001000>;
			phys = <&otgfs_phy>;
			status = "disabled";
		};
	};

	otgfs_phy: otgfs_phy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};