/* * Copyright (c) 2017 Intel Corporation. * * SPDX-License-Identifier: Apache-2.0 */ #include "skeleton.dtsi" #include #include #include / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "quark_x1000"; reg = <0>; }; intc: ioapic@fec00000 { compatible = "intel,ioapic"; reg = <0xfec00000 0x100000>; interrupt-controller; #interrupt-cells = <3>; }; }; flash0: flash@100000{ compatible = "soc-nv-flash"; reg = <0x00100000 DT_FLASH_SIZE>; }; sram0: memory@400000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0x00400000 DT_SRAM_SIZE>; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; uart0: uart@0 { compatible = "ns16550"; pcie; reg = ; label = "UART_0"; clock-frequency = <44236800>; interrupts = <0 IRQ_TYPE_LEVEL_LOW 0>; interrupt-parent = <&intc>; status = "disabled"; }; uart1: uart@1 { compatible = "ns16550"; pcie; reg = ; label = "UART_1"; clock-frequency = <44236800>; interrupts = <17 IRQ_TYPE_LEVEL_LOW 3>; interrupt-parent = <&intc>; status = "disabled"; }; i2c0: i2c@90007000 { compatible = "snps,designware-i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x90007000 0x400>; interrupts = <18 IRQ_TYPE_LEVEL_LOW 2>; interrupt-parent = <&intc>; label = "I2C_0"; status = "disabled"; }; spi0: spi@90009000 { compatible = "intel,intel-spi"; reg = <0x90009000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <16 IRQ_TYPE_EDGE_RISING 2>; interrupt-parent = <&intc>; label = "SPI_0"; status = "disabled"; }; spi1: spi@90008000 { compatible = "intel,intel-spi"; reg = <0x90008000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <17 IRQ_TYPE_EDGE_RISING 2>; interrupt-parent = <&intc>; label = "SPI_1"; status = "disabled"; }; }; sharedirq0: sharedirq0 { compatible = "shared-irq"; label = "SHARED_IRQ0"; interrupts = <18 IRQ_TYPE_LEVEL_LOW 2>; interrupt-parent = <&intc>; status = "disabled"; }; };