# Kconfig - XTENSA architecture configuration options # # Copyright (c) 2016 Cadence Design Systems, Inc. # SPDX-License-Identifier: Apache-2.0 choice prompt "XTENSA core Selection" depends on XTENSA source "arch/xtensa/soc/*/Kconfig.soc" endchoice menu "XTENSA Options" depends on XTENSA config ARCH default "xtensa" config SIMULATOR_XTENSA bool prompt "Simulator Configuration" default n help Specify if the board configuration should be treated as a simulator. config SYS_CLOCK_HW_CYCLES_PER_SEC int prompt "Hardware clock cycles per second, 2000000 for ISS" default 2000000 range 1000000 1000000000 help This option specifies hardware clock. config XTENSA_NO_IPC bool "Core has no IPC support" select ATOMIC_OPERATIONS_C default n help Uncheck this if you core does not implement "SCOMPARE1" register and "s32c1i" instruction. config SW_ISR_TABLE bool prompt "Enable software interrupt handler table" default y help Enable an interrupt handler table implemented in software. This table, unlike ISRs connected directly in the vector table, allow a parameter to be passed to the interrupt handlers. Also, invoking the exception/interrupt exit stub is automatically done. config XTENSA_RESET_VECTOR bool prompt "Build reset vector code" default y help This option controls whether the initial reset vector code is built. This is always needed for the simulator. Real boards may already implement this in boot ROM. config XTENSA_USE_CORE_CRT1 bool prompt "Use crt1.S from core" default y help SoC or boards might define their own __start by setting this setting to false. menu "Specific core configuration" config IRQ_OFFLOAD_INTNUM int prompt "IRQ offload SW interrupt index" help The index of the software interrupt to be used for IRQ offload. Please note that in order for IRQ offload to work correctly the selected interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL. config TOOLCHAIN_VARIANT string default RG-2016.4-linux source "arch/xtensa/soc/*/Kconfig" endmenu endmenu