/*
 * Copyright (c) 2018 Philémon Jaermann
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef __SENSOR_LSM303DLHC_ACCEL_
#define __SENSOR_LSM303DLHC_ACCEL_


#define LSM303_DLHC_ACCEL_X_EN_BIT	BIT(0)
#define LSM303DLHC_ACCEL_Y_EN_BIT	BIT(1)
#define LSM303DLHC_ACCEL_Z_EN_BIT	BIT(2)
#define LSM303DLHC_ACCEL_EN_BITS	(LSM303_DLHC_ACCEL_X_EN_BIT | \
					LSM303DLHC_ACCEL_Y_EN_BIT | \
					LSM303DLHC_ACCEL_Z_EN_BIT)

#if	(CONFIG_LSM303DLHC_ACCEL_POWER_MODE == 0)
	#define LSM303DLHC_LP_EN_BIT	0
#elif	(CONFIG_LSM303DLHC_ACCEL_POWER_MODE == 1)
	#define LSM303DLHC_LP_EN_BIT	BIT(3)
#endif

#define LSM303DLHC_ACCEL_ODR_SHIFT	4
#define LSM303DLHC_ACCEL_ODR_MASK   0xF0
#define LSM303DLHC_ACCEL_ODR_BITS	(CONFIG_LSM303DLHC_ACCEL_ODR << \
					LSM303DLHC_ACCEL_ODR_SHIFT)

#if     (CONFIG_LSM303DLHC_ACCEL_RANGE == 0)
	#define LSM303DLHC_ACCEL_SCALE	1
#elif	(CONFIG_LSM303DLHC_ACCEL_RANGE == 1)
	#define LSM303DLHC_ACCEL_SCALE	2
#elif	(CONFIG_LSM303DLHC_ACCEL_RANGE == 2)
	#define LSM303DLHC_ACCEL_SCALE	4
#elif	(CONFIG_LSM303DLHC_ACCEL_RANGE == 3)
	#define LSM303DLHC_ACCEL_SCALE	12
#endif

#define LSM303DLHC_ACCEL_AUTO_INC_ADDR	BIT(7)
#define LSM303DLHC_ACCEL_FS_SHIFT	4
#define LSM303DLHC_ACCEL_FS_BITS	(CONFIG_LSM303DLHC_ACCEL_RANGE << \
					LSM303DLHC_ACCEL_FS_SHIFT)

#define LSM303DLHC_REG_CTRL_1	0x20
#define LSM303DLHC_REG_CTRL_4	0x23
#define LSM303DLHC_REG_ACCEL_X_LSB	(0x28 | LSM303DLHC_ACCEL_AUTO_INC_ADDR)

enum lsm303dlhc_accel_odr {
    LSM303DLHC_ACCEL_ODR_1HZ,
    LSM303DLHC_ACCEL_ODR_10HZ,
    LSM303DLHC_ACCEL_ODR_25HZ,
    LSM303DLHC_ACCEL_ODR_50HZ,
    LSM303DLHC_ACCEL_ODR_100HZ,
    LSM303DLHC_ACCEL_ODR_200HZ,
    LSM303DLHC_ACCEL_ODR_400HZ,
    LSM303DLHC_ACCEL_ODR_1620HZ,
    LSM303DLHC_ACCEL_ODR_1344HZ,
    LSM303DLHC_ACCEL_ODR_5376HZ = LSM303DLHC_ACCEL_ODR_1344HZ,
};

struct lsm303dlhc_accel_data {
	struct device *i2c;

	s16_t accel_x;
	s16_t accel_y;
	s16_t accel_z;
};

struct lsm303dlhc_accel_config {
	char *i2c_name;
	u8_t i2c_address;
};
#endif /* __SENSOR_LSM303DLHC_ACCEL_ */