/*
 * Copyright 2022 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */


#include <nxp/nxp_imx7d_m4.dtsi>
#include <nxp/nxp_imx/mimx7d-pinctrl.dtsi>

&pinctrl {
	uart2_default: uart2_default {
		group0 {
			pinmux = <&mx7d_pad_uart2_rx_data__uart2_dte_tx>,
				<&mx7d_pad_uart2_tx_data__uart2_dte_rx>;
			bias-pull-up;
			bias-pull-up-value = "100k";
			input-schmitt-enable;
			slew-rate = "slow";
			drive-strength = "x1";
		};
	};

	uart6_default: uart6_default {
		group0 {
			pinmux = <&mx7d_pad_ecspi1_sclk__uart6_dce_rx>,
				<&mx7d_pad_ecspi1_mosi__uart6_dce_tx>;
			bias-pull-up;
			bias-pull-up-value = "100k";
			input-schmitt-enable;
			slew-rate = "slow";
			drive-strength = "x1";
		};
	};

	i2c1_default: i2c1_default {
		group0 {
			pinmux = <&mx7d_pad_i2c1_scl__i2c1_scl>,
				<&mx7d_pad_i2c1_sda__i2c1_sda>;
			bias-pull-up;
			bias-pull-up-value = "100k";
			input-schmitt-enable;
			slew-rate = "slow";
			drive-strength = "x1";
			input-enable;
		};
	};

	i2c2_default: i2c2_default {
		group0 {
			pinmux = <&mx7d_pad_i2c2_scl__i2c2_scl>,
				<&mx7d_pad_i2c2_sda__i2c2_sda>;
			bias-pull-up;
			bias-pull-up-value = "100k";
			input-schmitt-enable;
			slew-rate = "slow";
			drive-strength = "x1";
			input-enable;
		};
	};

	i2c3_default: i2c3_default {
		group0 {
			pinmux = <&mx7d_pad_i2c3_scl__i2c3_scl>,
				<&mx7d_pad_i2c3_sda__i2c3_sda>;
			bias-pull-up;
			bias-pull-up-value = "100k";
			input-schmitt-enable;
			slew-rate = "slow";
			drive-strength = "x1";
			input-enable;
		};
	};

	i2c4_default: i2c4_default {
		group0 {
			pinmux = <&mx7d_pad_i2c4_scl__i2c4_scl>,
				<&mx7d_pad_i2c4_sda__i2c4_sda>;
			bias-pull-up;
			bias-pull-up-value = "100k";
			input-schmitt-enable;
			slew-rate = "slow";
			drive-strength = "x1";
			input-enable;
		};
	};
};