# ARC options # # Copyright (c) 2014, 2019 Wind River Systems, Inc. # # SPDX-License-Identifier: Apache-2.0 # menu "ARC Options" depends on ARC config ARCH default "arc" choice prompt "ARC core family" default CPU_ARCEM config CPU_ARCEM bool "ARC EM cores" select CPU_ARCV2 select ATOMIC_OPERATIONS_C help This option signifies the use of an ARC EM CPU config CPU_ARCHS bool "ARC HS cores" select CPU_ARCV2 select ATOMIC_OPERATIONS_BUILTIN help This option signifies the use of an ARC HS CPU endchoice menu "ARCv2 Family Options" config CPU_ARCV2 bool select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || ARC_MPU select ARCH_HAS_USERSPACE if ARC_MPU select USE_SWITCH select USE_SWITCH_SUPPORTED default y help This option signifies the use of a CPU of the ARCv2 family. config DATA_ENDIANNESS_LITTLE bool default y help This is driven by the processor implementation, since it is fixed in hardware. The BSP should set this value to 'n' if the data is implemented as big endian. config NUM_IRQ_PRIO_LEVELS int "Number of supported interrupt priority levels" range 1 16 help Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The minimum value is 1. The BSP must provide a valid default for proper operation. config NUM_IRQS int "Upper limit of interrupt numbers/IDs used" range 17 256 help Interrupts available will be 0 to NUM_IRQS-1. The minimum value is 17 as the first 16 entries in the vector table are for CPU exceptions. The BSP must provide a valid default. This drives the size of the vector table. config RGF_NUM_BANKS int "Number of General Purpose Register Banks" depends on CPU_ARCV2 range 1 2 default 2 help The ARC CPU can be configured to have more than one register bank. If fast interrupts are supported (FIRQ), the 2nd register bank, in the set, will be used by FIRQ interrupts. If fast interrupts are supported but there is only 1 register bank, the fast interrupt handler must save and restore general purpose registers. config ARC_FIRQ bool "FIRQ enable" default y help Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts with highest priority, status32 and pc will be saved in aux regs, other regs will be saved according to the number of register bank; If FIRQ is disabled, the handle of interrupts with highest priority will be same with other interrupts. config ARC_HAS_STACK_CHECKING bool "ARC has STACK_CHECKING" default y help ARC is configured with STACK_CHECKING which is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected. config ARC_CONNECT bool "ARC has ARC connect" select SCHED_IPI_SUPPORTED help ARC is configured with ARC CONNECT which is a hardware for connecting multi cores. config ARC_STACK_CHECKING bool help Use ARC STACK_CHECKING to do stack protection config ARC_STACK_PROTECTION bool default y if HW_STACK_PROTECTION select ARC_STACK_CHECKING if ARC_HAS_STACK_CHECKING select MPU_STACK_GUARD if (!ARC_STACK_CHECKING && ARC_MPU) select THREAD_STACK_INFO help This option enables either: - The ARC stack checking, or - the MPU-based stack guard to cause a system fatal error if the bounds of the current process stack are overflowed. The two stack guard options are mutually exclusive. The selection of the ARC stack checking is prioritized over the MPU-based stack guard. config ARC_USE_UNALIGNED_MEM_ACCESS bool "Enable unaligned access in HW" default n if CPU_ARCEM default y if CPU_ARCHS depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS help ARC EM cores w/o secure shield 2+2 mode support might be configured to support unaligned memory access which is then disabled by default. Enable unaligned access in hardware and make software to use it. config FAULT_DUMP int "Fault dump level" default 2 range 0 2 help Different levels for display information when a fault occurs. 2: The default. Display specific and verbose information. Consumes the most memory (long strings). 1: Display general and short information. Consumes less memory (short strings). 0: Off. config XIP default y if !UART_NSIM config GEN_ISR_TABLES default y config GEN_IRQ_START_VECTOR default 16 config HARVARD bool "Harvard Architecture" help The ARC CPU can be configured to have two busses; one for instruction fetching and another that serves as a data bus. config CODE_DENSITY bool "Code Density Option" help Enable code density option to get better code density config ARC_HAS_ACCL_REGS bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" default y if FLOAT help Depending on the configuration, CPU can contain accumulator reg-pair (also referred to as r58:r59). These can also be used by gcc as GPR so kernel needs to save/restore per process config ARC_HAS_SECURE bool "ARC has SecureShield" select CPU_HAS_TEE select ARCH_HAS_TRUSTED_EXECUTION help This option is enabled when ARC core supports secure mode config SJLI_TABLE_SIZE int "SJLI table size" depends on ARC_SECURE_FIRMWARE default 8 help The size of sjli (Secure Jump and Link Indexed) table. The code in normal mode call secure services in secure mode through sjli instruction. config ARC_SECURE_FIRMWARE prompt "Generate Secure Firmware" bool depends on ARC_HAS_SECURE default y if TRUSTED_EXECUTION_SECURE help This option indicates that we are building a Zephyr image that is intended to execute in secure mode. The option is only applicable to ARC processors that implement the SecureShield. This option enables Zephyr to include code that executes in secure mode, as well as to exclude code that is designed to execute only in normal mode. Code executing in secure mode has access to both the secure and normal resources of the ARC processors. config ARC_NORMAL_FIRMWARE prompt "Generate Normal Firmware" bool depends on !ARC_SECURE_FIRMWARE depends on ARC_HAS_SECURE default y if TRUSTED_EXECUTION_NONSECURE help This option indicates that we are building a Zephyr image that is intended to execute in normal mode. Execution of this image is triggered by secure firmware that executes in secure mode. The option is only applicable to ARC processors that implement the SecureShield. This option enables Zephyr to include code that executes in normal mode only, as well as to exclude code that is designed to execute only in secure mode. Code executing in normal mode has no access to secure resources of the ARC processors, and, therefore, it shall avoid accessing them. menu "ARC MPU Options" depends on CPU_HAS_MPU config ARC_MPU_ENABLE bool "Enable MPU" select ARC_MPU help Enable MPU source "arch/arc/core/mpu/Kconfig" endmenu config CACHE_LINE_SIZE_DETECT bool "Detect d-cache line size at runtime" help This option enables querying the d-cache build register for finding the d-cache line size at the expense of taking more memory and code and a slightly increased boot time. If the CPU's d-cache line size is known in advance, disable this option and manually enter the value for CACHE_LINE_SIZE. config CACHE_LINE_SIZE int "Cache line size" if !CACHE_LINE_SIZE_DETECT default 32 help Size in bytes of a CPU d-cache line. Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT. config ARCH_CACHE_FLUSH_DETECT bool config CACHE_FLUSHING bool "Enable d-cache flushing mechanism" help This links in the sys_cache_flush() function, which provides a way to flush multiple lines of the d-cache. If the d-cache is present, set this to y. If the d-cache is NOT present, set this to n. config ARC_EXCEPTION_STACK_SIZE int "ARC exception handling stack size" default 768 help Size in bytes of exception handling stack which is at the top of interrupt stack to get smaller memory footprint because exception is not frequent. To reduce the impact on interrupt handling, especially nested interrupt, it cannot be too large. endmenu config ARC_EXCEPTION_DEBUG bool "Unhandled exception debugging information" default n depends on PRINTK || LOG help Print human-readable information about exception vectors, cause codes, and parameters, at a cost of code/data size for the human-readable strings. endmenu