/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <mem.h>
#include <st/u5/stm32u575.dtsi>

/ {
	sram0: memory@20000000 {
		/* SRAM1 + SRAM2 + SRAM3 */
		reg = <0x20000000 DT_SIZE_K(768)>;
	};

	soc {
		flash-controller@40022000 {
			flash0: flash@8000000 {
				reg = <0x08000000 DT_SIZE_M(2)>;
			};
		};
	};
};