/*
 * Copyright (c) 2024 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <nordic/nrf54l15.dtsi>

cpu: &cpuflpr {};
clic: &cpuflpr_clic {};

/delete-node/ &cpuapp;
/delete-node/ &cpuapp_rram;
/delete-node/ &cpuapp_ppb;
/delete-node/ &cpuapp_sram;

/ {
	soc {
		compatible = "simple-bus";
		interrupt-parent = <&cpuflpr_clic>;
		ranges;
	};
};

&cpuflpr {
	cpuflpr_vevif_rx: mailbox {
		compatible = "nordic,nrf-vevif-task-rx";
		status = "disabled";
		interrupt-parent = <&cpuflpr_clic>;
		interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>,
			     <17 NRF_DEFAULT_IRQ_PRIORITY>,
			     <18 NRF_DEFAULT_IRQ_PRIORITY>,
			     <19 NRF_DEFAULT_IRQ_PRIORITY>,
			     <20 NRF_DEFAULT_IRQ_PRIORITY>,
			     <21 NRF_DEFAULT_IRQ_PRIORITY>,
			     <22 NRF_DEFAULT_IRQ_PRIORITY>;
		#mbox-cells = <1>;
		nordic,tasks = <7>;
		nordic,tasks-mask = <0x007f0000>;
	};
};

&cpuflpr_vpr {
	cpuflpr_vevif_tx: mailbox {
		compatible = "nordic,nrf-vevif-event-tx";
		#mbox-cells = <1>;
		nordic,events = <1>;
		nordic,events-mask = <0x00100000>;
		status = "disabled";
	};
};

&cpuflpr_clic {
	status = "okay";
};

&grtc {
	interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
};

&gpiote20 {
	interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
};

&gpiote30 {
	interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
};