/*
 * Copyright (c) 2019, 2020 Antony Pavlov <antonynpavlov@gmail.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <st/l1/stm32l152.dtsi>

/ {
	sram0: memory@20000000 {
		reg = <0x20000000 DT_SIZE_K(80)>;
	};

	soc {
		flash-controller@40023c00 {
			flash0: flash@8000000 {
				reg = <0x08000000 DT_SIZE_K(512)>;
			};
		};

		timers5: timers@40000c00 {
			compatible = "st,stm32-timers";
			reg = <0x40000c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
			resets = <&rctl STM32_RESET(APB1, 3U)>;
			interrupts = <45 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		eeprom: eeprom@8080000{
			reg = <0x08080000 DT_SIZE_K(16)>;
		};

		rtc@40002800 {
			bbram: backup_regs {
				compatible = "st,stm32-bbram";
				st,backup-regs = <32>;
				status = "disabled";
			};
		};
	};
};