/*
 * Copyright (c) 2019 SEAL AG
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <nxp/nxp_kv5x.dtsi>

/ {
	/* 64KB ITCM @ 0, 64KB DTCM @ 20000000 */

	sram0: memory@20000000 {
		compatible = "mmio-sram";
		reg = <0x20000000 DT_SIZE_K(64)>;
	};
};

&flash_controller {
	flash0: flash@10000000 {
		compatible = "soc-nv-flash";
		label = "MCUX_FLASH";
		reg = <0x10000000 DT_SIZE_K(512)>;
		erase-block-size = <DT_SIZE_K(8)>;
		write-block-size = <8>;
	};
};