# Kconfig - Multilevel interrupt configuration
#
# Copyright (c) 2017 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#

config MULTI_LEVEL_INTERRUPTS
	bool "Multi-level Interrupts"
	depends on GEN_SW_ISR_TABLE
	help
	  Multiple levels of interrupts are normally used to increase the
	  number of addressable interrupts in a system. For e.g., if 2 levels
	  of interrupts are used, the 2nd level controller would combine all
	  interrupts routed to it into one line which then gets routed to one
	  of the lines in 1st level interrupt controller.

config MAX_IRQ_PER_AGGREGATOR
	int "Max IRQs per interrupt aggregator"
	default 0
	depends on MULTI_LEVEL_INTERRUPTS
	help
	  This represents the max number of interrupts that an aggregator
	  can map.

config 2ND_LEVEL_INTERRUPTS
	bool "Second-level Interrupts"
	depends on MULTI_LEVEL_INTERRUPTS
	help
	  Second level interrupts are used to increase the number of
	  addressable interrupts in a system.

config 2ND_LVL_ISR_TBL_OFFSET
	int "Offset in the SW ISR Table for 2nd level interrupt controller"
	default 0
	depends on MULTI_LEVEL_INTERRUPTS
	help
	  This is the offset in the SW ISR table beginning where the ISRs for
	  2nd level interrupts are located. This typically is allocated after
	  allocating first level interrupts.

config NUM_2ND_LEVEL_AGGREGATORS
	hex "Total Number of Second level Interrupt Aggregators"
	default 0
	depends on MULTI_LEVEL_INTERRUPTS
	help
	  This is the number of second level interrupt aggregators present
	  in the system. Each of these interrupt aggregators can typically
	  map MAX_IRQ_PER_AGGREGATOR second level interrupts to one first
	  level interrupt.

config 2ND_LVL_INTR_00_OFFSET
	hex "Parent interrupt number to which controller_0 maps"
	default 0x00
	depends on 2ND_LEVEL_INTERRUPTS
	help
	  This is the interrupt number in the first level to which
	  controller_0 of second level maps.

config 2ND_LVL_INTR_01_OFFSET
	hex "Parent interrupt number to which controller_1 maps"
	default 0x00
	depends on 2ND_LEVEL_INTERRUPTS
	help
	  This is the interrupt number in the first level to which
	  controller_1 of second level maps.

config 2ND_LVL_INTR_02_OFFSET
	hex "Parent interrupt number to which controller_2 maps"
	default 0x00
	depends on 2ND_LEVEL_INTERRUPTS
	help
	  This is the interrupt number in the first level to which
	  controller_2 of second level maps.

config 2ND_LVL_INTR_03_OFFSET
	hex "Parent interrupt number to which controller_3 maps"
	default 0x00
	depends on 2ND_LEVEL_INTERRUPTS
	help
	  This is the interrupt number in the first level to which
	  controller_3 of second level maps.

config 3RD_LEVEL_INTERRUPTS
	bool "Third-level Interrupts"
	depends on 2ND_LEVEL_INTERRUPTS
	help
	  Third level interrupts are used to increase the number of
	  addressable interrupts in a system.

config NUM_3RD_LEVEL_AGGREGATORS
	hex "Total Number of Third level Interrupt Aggregators"
	default 0
	depends on 3RD_LEVEL_INTERRUPTS
	help
	  These are the number of third level interrupt aggregators present
	  in the system. Each of these interrupt aggregators can typically
	  map MAX_IRQ_PER_AGGREGATOR third level interrupts to one second
	  level interrupt.

config 3RD_LVL_ISR_TBL_OFFSET
	int "Offset in the SW ISR Table for 3rd level interrupt controller"
	default 0
	depends on 3RD_LEVEL_INTERRUPTS
	help
	  This is the offset in the SW ISR table beginning where the ISRs for
	  3rd level interrupts are located. This typically is allocated after
	  allocating first and second level interrupts.

config 3RD_LVL_INTR_00_OFFSET
	hex "Parent interrupt number to which controller_0 maps"
	default 0x00
	depends on 3RD_LEVEL_INTERRUPTS
	help
	  This is the interrupt number in the second level to which
	  controller_0 of third level maps.