/*
 * Copyright (c) 2017, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <mem.h>
#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>

/ {
	aliases{
		gpio-0 = &gpio0;
		gpio-1 = &gpio1;
		mailbox-0 = &mailbox0;
	};

	chosen {
		zephyr,flash-controller = &iap;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m4f";
			reg = <0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-m0+";
			reg = <1>;
		};
	};

	soc {
		syscon: syscon@40000000 {
			compatible = "nxp,lpc-syscon";
			reg = <0x40000000 0x4000>;
			#clock-cells = <1>;
			reset: reset {
				compatible = "nxp,lpc-syscon-reset";
				#reset-cells = <1>;
			};
		};

		/*
		 * lpc54xxx Memory configurations:
		 * (note: reference manual says "up to <n>K")
		 * SRAM0 through SRAM3 will be contiguous
		 *
		 * LPC540xx: RAMX: 192K, SRAM0: 64K, SRAM1: 32K, SRAM2: 32K, SRAM3: 32K, USBRAM: 8K
		 * LPC5410x: RAMX: ----, SRAM0: 64K, SRAM1: 32K, USBRAM: 8K @ 0x03400000
		 * LPC5411x: RAMX: 32K,  SRAM0: 64K, SRAM1: 64K, SRAM2: 32K
		 *
		 * SRAM0-SRAM3 will be contiguous memory when present.
		 *
		 * The board level or application level device tree can override the memory sizes
		 * to allocate memory to the different cores of the dual-core platforms.
		 */
		sram0:memory@20000000 {
			compatible = "mmio-sram";
			reg = <0x20000000 DT_SIZE_K(64)>;
		};

		sram1:memory@20010000 {
			compatible = "zephyr,memory-region", "mmio-sram";
			reg = <0x20010000 DT_SIZE_K(64)>;
			zephyr,memory-region = "SRAM1";
		};

		sram2:memory@20020000 {
			compatible = "zephyr,memory-region", "mmio-sram";
			reg = <0x20020000 DT_SIZE_K(32)>;
			zephyr,memory-region = "SRAM2";
		};

		/*
		 * LPC54018: 192K @ 0x04000000
		 * LPC540xx: 192K @ 0x04000000
		 * LPC541xx:  32K @ 0x04000000
		 */
		sramx:memory@04000000{
			compatible = "mmio-sram";
			reg = <0x04000000 DT_SIZE_K(32)>;
		};

		iap: flash-controller@4009c000 {
			compatible = "nxp,iap-fmc54";
			reg = <0x4009c000 0x18>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
			flash0: flash@0 {
				compatible = "soc-nv-flash";
				reg = <0 DT_SIZE_K(256)>;
				erase-block-size = <256>;
				write-block-size = <256>;
			};
		};

		iocon: iocon@40001000 {
			compatible = "nxp,lpc-iocon";
			reg = <0x40001000 0x100>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x40001000 0x100>;
			pinctrl: pinctrl {
				compatible = "nxp,lpc-iocon-pinctrl";
			};
		};

		gpio: gpio@4008c000 {
			compatible = "nxp,lpc-gpio";
			reg = <0x4008c000 0x2488>;
			#address-cells = <1>;
			#size-cells = <0>;

			gpio0: gpio@0 {
				compatible = "nxp,lpc-gpio-port";
				reg = <0>;
				int-source = "pint";
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio1: gpio@1 {
				compatible = "nxp,lpc-gpio-port";
				reg = <1>;
				int-source = "pint";
				gpio-controller;
				#gpio-cells = <2>;
			};
		};

		pint: pint@40004000 {
			compatible = "nxp,pint";
			reg = <0x40004000 0x1000>;
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
				<32 2>, <33 2>, <34 2>, <35 2>;
			num-lines = <8>;
			num-inputs = <64>;
		};

		mailbox0:mailbox@4008b000 {
			compatible = "nxp,lpc-mailbox";
			reg = <0x4008b000 0xEC>;
			interrupts = <31 0>;
			status = "disabled";
		};

		flexcomm0: flexcomm@40086000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40086000 0x1000>;
			interrupts = <14 0>;
			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 11)>;
			status = "disabled";
		};

		flexcomm1: flexcomm@40087000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40087000 0x1000>;
			interrupts = <15 0>;
			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 12)>;
			status = "disabled";
		};

		flexcomm2: flexcomm@40088000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40088000 0x1000>;
			interrupts = <16 0>;
			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 13)>;
			status = "disabled";
		};

		flexcomm3: flexcomm@40089000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40089000 0x1000>;
			interrupts = <17 0>;
			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 14)>;
			status = "disabled";
		};

		flexcomm4: flexcomm@4008a000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x4008a000 0x1000>;
			interrupts = <18 0>;
			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 15)>;
			status = "disabled";
		};

		flexcomm5: flexcomm@40096000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40096000 0x1000>;
			interrupts = <19 0>;
			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 16)>;
			status = "disabled";
		};

		flexcomm6: flexcomm@40097000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40097000 0x1000>;
			interrupts = <20 0>;
			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 17)>;
			status = "disabled";
		};

		flexcomm7: flexcomm@40098000 {
			compatible = "nxp,lpc-flexcomm";
			reg = <0x40098000 0x1000>;
			interrupts = <21 0>;
			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
			resets = <&reset NXP_SYSCON_RESET(1, 18)>;
			status = "disabled";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};