#nRF UART(E) instance configuration

# Copyright (c) 2023 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0

config UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
	bool "Interrupt support on port $(nrfx_uart_num)"
	depends on UART_INTERRUPT_DRIVEN
	select UART_ASYNC_TO_INT_DRIVEN_API if !UART_NRFX_UARTE_LEGACY_SHIM
	default y
	help
	  This option enables UART interrupt support on port $(nrfx_uart_num).

config UART_$(nrfx_uart_num)_ASYNC
	bool "Asynchronous API support on port $(nrfx_uart_num)"
	depends on UART_ASYNC_API && !UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
	default y
	help
	  This option enables UART Asynchronous API support on port $(nrfx_uart_num).

config UART_$(nrfx_uart_num)_ENHANCED_POLL_OUT
	bool "Efficient poll out on port $(nrfx_uart_num)"
	default y
	depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
	select NRFX_PPI if HAS_HW_NRF_PPI
	select NRFX_DPPI if HAS_HW_NRF_DPPIC
	help
	  When enabled, polling out does not trigger interrupt which stops TX.
	  Feature uses a PPI channel.

config NRFX_UARTE$(nrfx_uart_num)
	def_bool y if HAS_HW_NRF_UARTE$(nrfx_uart_num) && !UART_NRFX_UARTE_LEGACY_SHIM

config UART_$(nrfx_uart_num)_NRF_PARITY_BIT
	bool "Parity bit"
	help
	  Enable parity bit.

config UART_$(nrfx_uart_num)_NRF_TX_BUFFER_SIZE
	int "Size of RAM buffer"
	depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
	depends on UART_NRFX_UARTE_LEGACY_SHIM
	range 1 65535
	default 32
	help
	  Size of the transmit buffer for API function: fifo_fill.
	  This value is limited by range of TXD.MAXCNT register for
	  particular SoC.

config UART_$(nrfx_uart_num)_NRF_HW_ASYNC
	bool "Use hardware RX byte counting"
	depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
	depends on UART_ASYNC_API
	depends on UART_NRFX_UARTE_LEGACY_SHIM
	select NRFX_PPI if HAS_HW_NRF_PPI
	select NRFX_DPPI if HAS_HW_NRF_DPPIC
	help
	  If default driver uses interrupts to count incoming bytes, it is possible
	  that with higher speeds and/or high cpu load some data can be lost.
	  It is recommended to use hardware byte counting in such scenarios.
	  Hardware RX byte counting requires timer instance and one PPI channel.

config UART_$(nrfx_uart_num)_NRF_ASYNC_LOW_POWER
	bool "Low power mode"
	depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
	depends on UART_ASYNC_API
	depends on UART_NRFX_UARTE_LEGACY_SHIM
	help
	  When enabled, UARTE is enabled before each TX or RX usage and disabled
	  when not used. Disabling UARTE while in idle allows to achieve lowest
	  power consumption. It is only feasible if receiver is not always on.

config UART_$(nrfx_uart_num)_NRF_HW_ASYNC_TIMER
	int "Timer instance"
	depends on UART_$(nrfx_uart_num)_NRF_HW_ASYNC

config UART_$(nrfx_uart_num)_TX_CACHE_SIZE
	int "TX cache buffer size"
	depends on !UART_NRFX_UARTE_LEGACY_SHIM
	default 8
	help
	  For UARTE, TX cache buffer is used when provided TX buffer is not located
	  in memory which can be used by the EasyDMA.

config UART_$(nrfx_uart_num)_RX_CACHE_SIZE
	int "RX cache buffer size"
	depends on !UART_NRFX_UARTE_LEGACY_SHIM
	default 32 if $(dt_nodelabel_has_compat,ram3x,$(DT_COMPAT_MMIO_SRAM))
	default 5
	range 5 255
	help
	  For UARTE, RX cache buffer is used when provided RX buffer is not located
	  in memory which can be used by the EasyDMA. It is also used to store
	  flushed data.

config UART_$(nrfx_uart_num)_A2I_RX_SIZE
	depends on !UART_NRFX_UARTE_LEGACY_SHIM
	int "Asynchronous to interrupt driven adaptation layer RX buffer size"
	default 64 if UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
	default 0
	help
	  Amount of space dedicated for RX. It is divided into chunks with some
	  amount of that space used for control data.

config UART_$(nrfx_uart_num)_A2I_RX_BUF_COUNT
	depends on !UART_NRFX_UARTE_LEGACY_SHIM
	int "Asynchronous to interrupt driven adaptation layer RX buffer count"
	default 8 if UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
	default 0
	help
	  Number of chunks into RX space is divided.

config UART_$(nrfx_uart_num)_GPIO_MANAGEMENT
	bool "GPIO management on port $(nrfx_uart_num)"
	depends on PM_DEVICE
	default y
	help
	  If enabled, the driver will configure the GPIOs used by the uart to
	  their default configuration when device is powered down. The GPIOs
	  will be configured back to correct state when UART is powered up.