/*
 * Copyright (c) 2024, Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <intel/intel_socfpga_agilex5.dtsi>

/ {
	model = "Intel SoC FPGA Agilex5";
	compatible = "intel,socfpga-agilex5";
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
		zephyr,sram = &mem0;
	};
};

&sdmmc {
	status = "okay";
	mmc {
		/*SD Disk Access */
		compatible = "zephyr,sdmmc-disk";
		disk-name = "SD";
		status = "okay";
	};
};

&uart0 {
	status = "okay";
	current-speed = <115200>;
};

&xgmac0 {
	full-duplex-mode-en;
	num-dma-ch   = <1>;
	num-tx-queues = <1>;
	num-rx-queues = <1>;
	num-tc = <1>;
	dma-ch-rdrl = <128>;
	dma-ch-tdrl = <128>;
	max-speed = <1000>;
	max-frame-size = <9018>;
	jumbo-pkt-en;
	zephyr,random-mac-address;
	phy-handle = <&phy0>;
};

&mdio0  {
	csr-clock-indx = <4>;

	phy0: phy@0 {
		compatible = "ethernet-phy";
		reg = <0>;
	};
};