/* * Copyright (c) 2022 Benjamin Björnsson . * Copyright (c) 2024 DNDG srl * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; #include #include #include #include "arduino_opta-common.dtsi" / { model = "Arduino OPTA M7 core Programmable Logic Controller"; compatible = "arduino,opta-m7"; chosen { zephyr,console = &cdc_acm_uart0; zephyr,shell-uart = &cdc_acm_uart0; zephyr,cdc-acm-uart0 = &cdc_acm_uart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; }; ethernet_phy_en: ethernet_phy_en { compatible = "regulator-fixed"; regulator-name = "ethernet-phy-reset-release"; enable-gpios = <&gpioj 15 GPIO_ACTIVE_HIGH>; regulator-boot-on; status = "okay"; }; sdram2: sdram@d0000000 { compatible = "zephyr,memory-region", "mmio-sram"; device_type = "memory"; reg = <0xd0000000 DT_SIZE_M(32)>; zephyr,memory-region = "SDRAM2"; zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; }; }; zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; status = "okay"; cdc_acm_uart0: cdc_acm_uart0 { compatible = "zephyr,cdc-acm-uart"; }; }; &clk_hse { clock-frequency = ; hse-bypass; status = "okay"; }; &clk_lse { clock-frequency = <32768>; lse-bypass; status = "okay"; }; &clk_hsi { hsi-div = <1>; status = "okay"; }; &clk_hsi48 { /* HSI48 required for USB */ status = "okay"; }; &pll { div-m = <5>; mul-n = <160>; div-p = <2>; div-r = <2>; div-q = <10>; clocks = <&clk_hse>; status = "okay"; }; &rcc { clocks = <&pll>; clock-frequency = ; }; &flash0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; slot0_partition: partition@40000 { label = "image-0"; reg = <0x00040000 DT_SIZE_K(768)>; }; }; }; &usbotg_fs { status = "okay"; }; &usbotg_hs { status = "disabled"; }; &cdc_acm_uart0 { status = "okay"; }; &mac { pinctrl-0 = < ð_ref_clk_pa1 ð_crs_dv_pa7 ð_rxd0_pc4 ð_rxd1_pc5 ð_tx_en_pg11 ð_txd1_pg12 ð_txd0_pg13 >; pinctrl-names = "default"; status = "okay"; }; &mdio { status = "okay"; pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; pinctrl-names = "default"; ethernet-phy@0 { compatible = "ethernet-phy"; reg = <0x00>; status = "okay"; }; }; &rng { status = "okay"; };