# Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 config SOC_FAMILY_NXP_IMXRT select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE if SOC_FAMILY_NXP_IMXRT # Source series Kconfig files first, so SOCs # can override the defaults given here rsource "*/Kconfig" # Used for default value in FLASH_MCUX_FLEXSPI_XIP DT_CHOSEN_Z_FLASH := zephyr,flash DT_COMPAT_FLEXSPI := nxp,imx-flexspi # Macros to shorten Kconfig definitions DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) config FLASH_MCUX_FLEXSPI_XIP bool "MCUX FlexSPI flash access with xip" default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) select XIP help Allows for the soc to safely initialize the clocks for the FlexSpi when planning to execute code in FlexSpi Memory. if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET prompt "FlexSPI drivers relocation target" default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM help Select the location to run the FlexSPI drivers when using the flash API. config FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM bool "ITCM" select CODE_DATA_RELOCATION config FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM bool "RAM" select CODE_DATA_RELOCATION_SRAM endchoice config FLASH_MCUX_FLEXSPI_XIP_MEM string default "ITCM" if FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI # Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig # should be set elsewhere, since the determination of which SOC core # requires the boot header is SOC specific. config NXP_IMXRT_BOOT_HEADER bool "Boot header" default y depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX) help Enable data structures required by the boot ROM to boot the application from an external flash device. if NXP_IMXRT_BOOT_HEADER choice BOOT_DEVICE prompt "Boot device" default BOOT_FLEXSPI_NOR config BOOT_FLEXSPI_NOR bool "FlexSPI serial NOR" depends on HAS_MCUX_FLEXSPI config BOOT_FLEXSPI_NAND bool "FlexSPI serial NAND" depends on HAS_MCUX_FLEXSPI config BOOT_SEMC_NOR bool "SEMC parallel NOR" depends on HAS_MCUX_SEMC config BOOT_SEMC_NAND bool "SEMC parallel NAND" depends on HAS_MCUX_SEMC endchoice # BOOT_DEVICE config FLEXSPI_CONFIG_BLOCK_OFFSET hex "FlexSPI config block offset" default 0x400 if SOC_SERIES_IMXRT5XX || SOC_SERIES_IMXRT6XX || SOC_MIMXRT1011 default 0x0 if BOOT_FLEXSPI_NOR help FlexSPI configuration block consists of parameters regarding specific flash devices including read command sequence, quad mode enablement sequence (optional), etc. The boot ROM expects FlexSPI configuration parameter to be presented in serial nor flash. config IMAGE_VECTOR_TABLE_OFFSET hex "Image vector table offset" default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND help The Image Vector Table (IVT) provides the boot ROM with pointers to the application entry point and device configuration data. The boot ROM requires a fixed IVT offset for each type of boot device. config DEVICE_CONFIGURATION_DATA bool "Device configuration data" help Device configuration data (DCD) provides a sequence of commands to the boot ROM to initialize components such as an SDRAM. This is useful if your application expects components like SDRAM to be initialized at boot time. endif # NXP_IMXRT_BOOT_HEADER config NXP_IMX_EXTERNAL_SDRAM bool "Allow access to external SDRAM region" help Enable access to external SDRAM region managed by the SEMC. This setting should be enabled when the application uses SDRAM, or an MPU region will be defined to disable cached access to the SDRAM memory space. config NXP_IMX_RT_ROM_RAMLOADER depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMXRT_BOOT_HEADER # Required so that debugger will load image to correct offset select BUILD_OUTPUT_HEX bool "Create output image that IMX RT ROM can load from FlexSPI to ram" help Builds an output image that the IMX RT BootROM can load from the FlexSPI boot device into RAM region. The image will be loaded from FLEXSPI into the region specified by `zephyr,flash` node. # Setup LMA adjustment if using the RAMLOADER feature of ROM FLASH_CHOSEN := zephyr,flash FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) config BUILD_OUTPUT_ADJUST_LMA default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER config SECOND_CORE_MCUX bool "Dual core operation on the RT11xx series" depends on SOC_SERIES_IMXRT11XX help Indicates the second core will be enabled, and the part will run in dual core mode. Enables dual core operation on the RT11xx series, by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. The M4 image will be loaded from flash into RAM based off a generated header specifying the VMA and LMA of each memory section to load config FLEXSPI_CONFIG_BLOCK_OFFSET hex default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX config PM_MCUX_GPC bool "MCUX general power controller driver" config PM_MCUX_DCDC bool "MCUX dcdc converter module driver" config PM_MCUX_PMU bool "MCUX power management unit driver" config DCDC_VALUE hex "DCDC value for VDD_SOC" config INIT_ARM_PLL bool "Initialize ARM PLL" config INIT_VIDEO_PLL bool "Initialize Video PLL" config INIT_ENET_PLL bool help If y, the Ethernet PLL is initialized. Always enabled on e.g. MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection for MIMXRT1021"). endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX endif # SOC_FAMILY_NXP_IMXRT