/* * Copyright (c) 2017 Linaro Limited * * SPDX-License-Identifier: Apache-2.0 */ #include #include #include #include #include / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m4f"; reg = <0>; }; }; sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; soc { flash-controller@40022000 { compatible = "st,stm32l4-flash-controller"; label = "FLASH_CTRL"; reg = <0x40022000 0x400>; interrupts = <4 0>; #address-cells = <1>; #size-cells = <1>; flash0: flash@8000000 { compatible = "soc-nv-flash"; label = "FLASH_STM32"; write-block-size = <8>; erase-block-size = <2048>; }; }; rcc: rcc@40021000 { compatible = "st,stm32-rcc"; clocks-controller; #clock-cells = <2>; reg = <0x40021000 0x400>; label = "STM32_CLK_RCC"; }; pinctrl: pin-controller@48000000 { compatible = "st,stm32-pinmux"; #address-cells = <1>; #size-cells = <1>; reg = <0x48000000 0x2000>; gpioa: gpio@48000000 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>; label = "GPIOA"; }; gpiob: gpio@48000400 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>; label = "GPIOB"; }; gpioc: gpio@48000800 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>; label = "GPIOC"; }; gpioh: gpio@48001c00 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>; label = "GPIOH"; }; }; iwdg: watchdog@40003000 { compatible = "st,stm32-watchdog"; reg = <0x40003000 0x400>; label = "IWDG"; status = "disabled"; }; usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; interrupts = <37 0>; status = "disabled"; label = "UART_1"; }; usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; interrupts = <38 0>; status = "disabled"; label = "UART_2"; }; lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>; interrupts = <70 0>; status = "disabled"; label = "LPUART_1"; }; i2c1: i2c@40005400 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_1"; }; i2c3: i2c@40005c00 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x40005c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_3"; }; spi1: spi@40013000 { compatible = "st,stm32-spi-fifo"; #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <35 5>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; status = "disabled"; label = "SPI_1"; }; timers1: timers@40012c00 { compatible = "st,stm32-timers"; reg = <0x40012c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; status = "disabled"; label = "TIMERS_1"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_1"; #pwm-cells = <2>; }; }; timers2: timers@40000000 { compatible = "st,stm32-timers"; reg = <0x40000000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; status = "disabled"; label = "TIMERS_2"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <0>; label = "PWM_2"; #pwm-cells = <2>; }; }; timers6: timers@40001000 { compatible = "st,stm32-timers"; reg = <0x40001000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; status = "disabled"; label = "TIMERS_6"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_6"; #pwm-cells = <2>; }; }; timers7: timers@40001400 { compatible = "st,stm32-timers"; reg = <0x40001400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; status = "disabled"; label = "TIMERS_7"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_7"; #pwm-cells = <2>; }; }; timers15: timers@40014000 { compatible = "st,stm32-timers"; reg = <0x40014000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>; status = "disabled"; label = "TIMERS_15"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_15"; #pwm-cells = <2>; }; }; timers16: timers@40014400 { compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>; status = "disabled"; label = "TIMERS_16"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_16"; #pwm-cells = <2>; }; }; can1: can@40006400 { compatible = "st,stm32-can"; #address-cells = <1>; #size-cells = <0>; reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN status = "disabled"; label = "CAN_1"; bus-speed = <125000>; sjw = <1>; prop_seg_phase_seg1 = <4>; phase_seg2 = <5>; }; rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; interrupts = <41 0>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>; prescaler = <32768>; status = "disabled"; label = "RTC_0"; }; adc1: adc@50040000 { compatible = "st,stm32-adc"; reg = <0x50040000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>; interrupts = <18 0>; status = "disabled"; label = "ADC_1"; }; }; }; &nvic { arm,num-irq-priority-bits = <4>; };