# Copyright (c) 2020 Cobham Gaisler AB # Copyright (c) 2024 Antmicro # SPDX-License-Identifier: Apache-2.0 if SOC_FAMILY_QEMU_VIRT_RISCV config SYS_CLOCK_HW_CYCLES_PER_SEC default 10000000 config RISCV_SOC_INTERRUPT_INIT default y config RISCV_GP default y config 2ND_LVL_ISR_TBL_OFFSET default 12 config 2ND_LVL_INTR_00_OFFSET default 11 config 2ND_LEVEL_INTERRUPT_BITS default 11 config MAX_IRQ_PER_AGGREGATOR default 1024 config NUM_IRQS default 1036 config PMP_SLOTS default 16 endif # SOC_FAMILY_QEMU_VIRT_RISCV