/* * Copyright (c) 2021 Guðni Már Gilbert * * SPDX-License-Identifier: Apache-2.0 */ #include / { soc { timers5: timers@40000c00 { compatible = "st,stm32-timers"; reg = <0x40000c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; interrupts = <50 0>; interrupt-names = "global"; st,prescaler = <0>; status = "disabled"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; #pwm-cells = <3>; }; }; adc4: adc@50000500 { compatible = "st,stm32-adc"; reg = <0x50000500 0x100>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>; interrupts = <61 0>; status = "disabled"; #io-channel-cells = <1>; }; adc5: adc@50000600 { compatible = "st,stm32-adc"; reg = <0x50000600 0x100>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>; interrupts = <62 0>; status = "disabled"; #io-channel-cells = <1>; has-temp-channel; }; spi4: spi@40013c00 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40013c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>; interrupts = <84 5>; status = "disabled"; }; dac2: dac@50000c00 { compatible = "st,stm32-dac"; reg = <0x50000c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00020000>; status = "disabled"; #io-channel-cells = <1>; }; dac4: dac@50001400 { compatible = "st,stm32-dac"; reg = <0x50001400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00080000>; status = "disabled"; #io-channel-cells = <1>; }; i2c4: i2c@40008400 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x40008400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>; interrupts = <82 0>, <83 0>; interrupt-names = "event", "error"; status = "disabled"; }; can { can3: can@40006C00 { compatible = "st,stm32-fdcan"; reg = <0x40006C00 0x400>, <0x4000AAA0 0x350>; reg-names = "m_can", "message_ram"; interrupts = <88 0>, <89 0>; interrupt-names = "LINE_0", "LINE_1"; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; status = "disabled"; sjw = <1>; sample-point = <875>; sjw-data = <1>; sample-point-data = <875>; }; }; }; };