/*
 * Copyright (c) 2021 Yonatan Schachter
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY
#define RPI_PICO_DEFAULT_IRQ_PRIORITY 3
#endif

#define RPI_PICO_RESETS_RESET_ADC		0
#define RPI_PICO_RESETS_RESET_BUSCTRL		1
#define RPI_PICO_RESETS_RESET_DMA		2
#define RPI_PICO_RESETS_RESET_I2C0		3
#define RPI_PICO_RESETS_RESET_I2C1		4
#define RPI_PICO_RESETS_RESET_IO_BANK0		5
#define RPI_PICO_RESETS_RESET_IO_QSPI		6
#define RPI_PICO_RESETS_RESET_JTAG		7
#define RPI_PICO_RESETS_RESET_PADS_BANK0	8
#define RPI_PICO_RESETS_RESET_PADS_QSPI		9
#define RPI_PICO_RESETS_RESET_PIO0		10
#define RPI_PICO_RESETS_RESET_PIO1		11
#define RPI_PICO_RESETS_RESET_PLL_SYS		12
#define RPI_PICO_RESETS_RESET_PLL_USB		13
#define RPI_PICO_RESETS_RESET_PWM		14
#define RPI_PICO_RESETS_RESET_RTC		15
#define RPI_PICO_RESETS_RESET_SPI0		16
#define RPI_PICO_RESETS_RESET_SPI1		17
#define RPI_PICO_RESETS_RESET_SYSCFG		18
#define RPI_PICO_RESETS_RESET_SYSINFO		19
#define RPI_PICO_RESETS_RESET_TBMAN		20
#define RPI_PICO_RESETS_RESET_TIMER		21
#define RPI_PICO_RESETS_RESET_UART0		22
#define RPI_PICO_RESETS_RESET_UART1		23
#define RPI_PICO_RESETS_RESET_USBCTRL		24