# Kconfig - SPI driver configuration options # # Copyright (c) 2015 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # # # SPI Drivers # menuconfig SPI bool prompt "SPI hardware bus support" default n help Enable support for the SPI hardware bus. if SPI config SPI_DEBUG bool prompt "SPI drivers debug output" depends on SPI default n help Enable debug output for SPI drivers config SPI_INTEL bool prompt "Intel SPI controller driver" depends on SPI && CPU_MINUTEIA default n help Enable support for Intel's SPI controllers. Such controller was formelly found on XScale chips. It can be found nowadays on CEXXXX Intel media controller and Quark CPU (2 of them). choice depends on SPI_INTEL prompt "Intel SPI interrupt trigger condition" default SPI_INTEL_RISING_EDGE config SPI_INTEL_FALLING_EDGE bool "Falling edge" help "Intel SPI uses falling edge interrupt" config SPI_INTEL_RISING_EDGE bool "Rising edge" help "Intel SPI uses rising edge interrupt" config SPI_INTEL_LEVEL_HIGH bool "Level high" help "Intel SPI uses level high interrupt" config SPI_INTEL_LEVEL_LOW bool "Level low" help "Intel SPI uses level low interrupt" endchoice config SPI_INTEL_VENDOR_ID hex "PCI Vendor ID" depends on SPI_INTEL && PCI default 0x8086 config SPI_INTEL_DEVICE_ID hex "PCI Device ID" depends on SPI_INTEL && PCI default 0x935 config SPI_INTEL_CLASS hex "PCI class" depends on SPI_INTEL && PCI default 0x0C config SPI_INTEL_CS_GPIO bool "SPI port CS pin is controlled via a GPIO port" depends on SPI_INTEL && GPIO default n config SPI_INTEL_INIT_PRIORITY int prompt "Init priority" depends on SPI_INTEL default 60 help Device driver initialization priority. config SPI_INTEL_PORT_0 bool prompt "Intel SPI port 0" depends on SPI_INTEL default n help Enable Intel's SPI controller port 0. config SPI_INTEL_PORT_0_DRV_NAME string prompt "Intel SPI port 0 device name" depends on SPI_INTEL_PORT_0 default "intel_spi_0" config SPI_INTEL_PORT_0_BUS int "Port 0 PCI Bus" depends on SPI_INTEL_PORT_0 && PCI default 0 config SPI_INTEL_PORT_0_DEV int "Port 0 PCI Dev" depends on SPI_INTEL_PORT_0 && PCI default 0 config SPI_INTEL_PORT_0_FUNCTION int "Port 0 PCI function" depends on SPI_INTEL_PORT_0 && PCI default 0 config SPI_INTEL_PORT_0_REGS hex prompt "Port 0 registers address" depends on SPI_INTEL_PORT_0 default 0x00000000 config SPI_INTEL_PORT_0_IRQ int prompt "Port 0 interrupt" depends on SPI_INTEL_PORT_0 default 0 config SPI_INTEL_PORT_0_PRI int prompt "Port 0 interrupt priority" depends on SPI_INTEL_PORT_0 default 2 config SPI_INTEL_PORT_0_CS_GPIO_PORT string prompt "The GPIO port which is used to control CS" depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO default GPIO_DW_0_NAME config SPI_INTEL_PORT_0_CS_GPIO_PIN int "The GPIO PIN which is used to act as a CS pin" depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO default 0 config SPI_INTEL_PORT_1 bool prompt "Intel SPI port 1" depends on SPI_INTEL default n help Enable Intel's SPI controller port 1. config SPI_INTEL_PORT_1_DRV_NAME string prompt "Intel SPI port 1 device name" depends on SPI_INTEL_PORT_1 default "intel_spi_1" config SPI_INTEL_PORT_1_BUS int "Port 1 PCI Bus" depends on SPI_INTEL_PORT_1 && PCI default 0 config SPI_INTEL_PORT_1_DEV int "Port 1 PCI Dev" depends on SPI_INTEL_PORT_1 && PCI default 0 config SPI_INTEL_PORT_1_FUNCTION int "Port 1 PCI function" depends on SPI_INTEL_PORT_1 && PCI default 0 config SPI_INTEL_PORT_1_REGS hex prompt "Port 1 registers address" depends on SPI_INTEL_PORT_1 default 0x00000000 config SPI_INTEL_PORT_1_IRQ int prompt "Port 1 interrupt" depends on SPI_INTEL_PORT_1 default 0 config SPI_INTEL_PORT_1_PRI int prompt "Port 0 interrupt priority" depends on SPI_INTEL_PORT_1 default 2 config SPI_INTEL_PORT_1_CS_GPIO_PORT string prompt "The GPIO port which is used to control CS" depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO default GPIO_DW_0_NAME config SPI_INTEL_PORT_1_CS_GPIO_PIN int "The GPIO PIN which is used to act as a CS pin" depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO default 0 config SPI_DW bool prompt "Designware SPI controller driver" depends on SPI default n help Enable support for Designware's SPI controllers. config SPI_DW_ARC_AUX_REGS bool "Registers are part of ARC auxiliary registers" depends on SPI_DW && ARC default y help SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers. config SPI_DW_CS_GPIO bool "SPI port CS pin is controlled via a GPIO port" depends on SPI_DW && GPIO default n config SPI_DW_INIT_PRIORITY int "Init priority" default 60 help Device driver initialization priority. choice depends on SPI_DW prompt "DesignWare SPI interrupt trigger condition" default SPI_DW_RISING_EDGE config SPI_DW_FALLING_EDGE bool "Falling edge" help "DesignWare SPI uses falling edge interrupt" config SPI_DW_RISING_EDGE bool "Rising edge" help "DesignWare SPI uses rising edge interrupt" config SPI_DW_LEVEL_HIGH bool "Level high" help "DesignWare SPI uses level high interrupt" config SPI_DW_LEVEL_LOW bool "Level low" help "DesignWare SPI uses level low interrupt" endchoice config SPI_DW_CLOCK_GATE bool "Enable glock gating" depends on SPI_DW && SOC_QUARK_SE select CLOCK_CONTROL default n config SPI_DW_CLOCK_GATE_DRV_NAME string depends on SPI_DW_CLOCK_GATE default "" config SPI_DW_PORT_0 bool prompt "Designware SPI port 0" depends on SPI_DW default n help Enable Designware SPI controller port 0. config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" depends on SPI_DW_CLOCK_GATE default 0 config SPI_DW_PORT_0_CS_GPIO_PORT string prompt "The GPIO port which is used to control CS" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default GPIO_DW_0_NAME config SPI_DW_PORT_0_CS_GPIO_PIN int "The GPIO PIN which is used to act as a CS pin" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default 0 config SPI_DW_PORT_0_DRV_NAME string prompt "Designware SPI port 0 device name" depends on SPI_DW_PORT_0 default "spi_dw_0" config SPI_DW_PORT_0_REGS hex prompt "Port 0 registers address" depends on SPI_DW_PORT_0 default 0x00000000 config SPI_DW_PORT_0_IRQ int prompt "Port 0 interrupt" depends on SPI_DW_PORT_0 default 0 config SPI_DW_PORT_0_PRI int prompt "Port 0 interrupt priority" depends on SPI_DW_PORT_0 default 2 config SPI_DW_PORT_1 bool prompt "Designware SPI port 1" depends on SPI_DW default n help Enable Designware SPI controller port 1. config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" depends on SPI_DW_CLOCK_GATE default 0 config SPI_DW_PORT_1_CS_GPIO_PORT string prompt "The GPIO port which is used to control CS" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default GPIO_DW_0_NAME config SPI_DW_PORT_1_CS_GPIO_PIN int "The GPIO PIN which is used to act as a CS pin" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default 0 config SPI_DW_PORT_1_DRV_NAME string prompt "Designware SPI port 1 device name" depends on SPI_DW_PORT_1 default "spi_dw_1" config SPI_DW_PORT_1_REGS hex prompt "Port 1 registers address" depends on SPI_DW_PORT_1 default 0x00000000 config SPI_DW_PORT_1_IRQ int prompt "Port 1 interrupt" depends on SPI_DW_PORT_1 default 0 config SPI_DW_PORT_1_PRI int prompt "Port 0 interrupt priority" depends on SPI_DW_PORT_1 default 2 endif