# Kconfig.dw - DesignWare SPI driver configuration options
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# Copyright (c) 2015-2016 Intel Corporation
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# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
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#     http://www.apache.org/licenses/LICENSE-2.0
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menuconfig SPI_DW
	bool
	prompt "Designware SPI controller driver"
	depends on SPI
	default n
	help
	  Enable support for Designware's SPI controllers.

if SPI_DW

config SPI_DW_ARC_AUX_REGS
	bool "Registers are part of ARC auxiliary registers"
	depends on SPI_DW && ARC
	default y
	help
	  SPI IP block registers are part of user extended auxiliary
	  registers and thus their access is different than memory
	  mapped registers.


choice
depends on SPI_DW
prompt "DesignWare SPI interrupt management logic"
default SPI_DW_INTERRUPT_SINGLE_LINE

config SPI_DW_INTERRUPT_SINGLE_LINE
	bool "Single interrupt line for all interrupts"
	help
	  Only one line is used to trigger interrupts: RX, TX and ERROR
	  interrupt go all through that line, undifferentiated.
config SPI_DW_INTERRUPT_SEPARATED_LINES
	bool "One line per-interrupt type (RX, TX and ERROR)"
	help
	  Each interrupt gets a dedicated line
endchoice

config SPI_DW_CLOCK_GATE
	bool "Enable glock gating"
	depends on SPI_DW && SOC_QUARK_SE_C1000
	select CLOCK_CONTROL
	default n

config	SPI_DW_CLOCK_GATE_DRV_NAME
	string
	depends on SPI_DW_CLOCK_GATE
	default ""

config SPI_DW_FIFO_DEPTH
	int "Rx and Tx FIFO Depth"
	help
	  Corresponds to the SSI_TX_FIFO_DEPTH and
	  SSI_RX_FIFO_DEPTH of the DesignWare Syncrhonous
	  Serial Interface. Depth ranges from 2-256.

config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
	int "Clock controller's subsystem"
	depends on SPI_DW_CLOCK_GATE


config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
	int "Clock controller's subsystem"
	depends on SPI_DW_CLOCK_GATE


endif # SPI_DW