/* * Copyright 2022 NXP * * SPDX-License-Identifier: Apache-2.0 */ #include #include #include #include #include / { #address-cells = <1>; #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0>; }; cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x100>; }; }; arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , , , ; interrupt-parent = <&gic>; }; gic: interrupt-controller@48000000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0x48000000 0x10000>, /* GIC Dist */ <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; }; iomuxc: iomuxc@443c0000 { compatible = "nxp,imx-iomuxc"; reg = <0x443c0000 DT_SIZE_K(64)>; status = "okay"; pinctrl: pinctrl { status = "okay"; compatible = "nxp,imx93-pinctrl"; }; }; ana_pll: ana_pll@44480000 { compatible = "nxp,imx-ana"; reg = <0x44480000 DT_SIZE_K(64)>; }; ccm: ccm@44450000 { compatible = "nxp,imx-ccm-rev2"; reg = <0x44450000 DT_SIZE_K(64)>; #clock-cells = <3>; }; lpuart1: serial@44380000 { compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart"; reg = <0x44380000 DT_SIZE_K(64)>; interrupts = ; interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_LPUART1_CLK 0x6c 24>; status = "disabled"; }; lpuart2: serial@44390000 { compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart"; reg = <0x44390000 DT_SIZE_K(64)>; interrupts = ; interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>; status = "disabled"; }; };