/* * Copyright (c) 2020 Alexander Mihajlovic * * SPDX-License-Identifier: Apache-2.0 */ #include / { soc { compatible = "st,stm32l071", "st,stm32l0", "simple-bus"; pinctrl: pin-controller@50000000 { gpioe: gpio@50001000 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x50001000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>; }; }; i2c2: i2c@40005800 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; }; i2c3: i2c@40007800 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x40007800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>; interrupts = <21 0>; interrupt-names = "combined"; status = "disabled"; }; spi2: spi@40003800 { compatible = "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; interrupts = <26 3>; status = "disabled"; }; timers3: timers@40000400 { compatible = "st,stm32-timers"; reg = <0x40000400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; resets = <&rctl STM32_RESET(APB1, 1U)>; interrupts = <16 0>; interrupt-names = "global"; st,prescaler = <0>; status = "disabled"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; #pwm-cells = <3>; }; counter { compatible = "st,stm32-counter"; status = "disabled"; }; }; timers6: timers@40001000 { compatible = "st,stm32-timers"; reg = <0x40001000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; resets = <&rctl STM32_RESET(APB1, 4U)>; interrupts = <17 0>; interrupt-names = "global"; st,prescaler = <0>; status = "disabled"; counter { compatible = "st,stm32-counter"; status = "disabled"; }; }; timers7: timers@40001400 { compatible = "st,stm32-timers"; reg = <0x40001400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; resets = <&rctl STM32_RESET(APB1, 5U)>; interrupts = <18 0>; interrupt-names = "global"; st,prescaler = <0>; status = "disabled"; counter { compatible = "st,stm32-counter"; status = "disabled"; }; }; timers22: timers@40011400 { compatible = "st,stm32-timers"; reg = <0x40011400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>; resets = <&rctl STM32_RESET(APB2, 5U)>; interrupts = <22 0>; interrupt-names = "global"; st,prescaler = <0>; status = "disabled"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; #pwm-cells = <3>; }; counter { compatible = "st,stm32-counter"; status = "disabled"; }; }; usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; resets = <&rctl STM32_RESET(APB2, 14U)>; interrupts = <27 0>; status = "disabled"; }; usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; resets = <&rctl STM32_RESET(APB1, 19U)>; interrupts = <14 0>; status = "disabled"; }; usart5: serial@40005000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40005000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; resets = <&rctl STM32_RESET(APB1, 20U)>; interrupts = <14 0>; status = "disabled"; }; eeprom: eeprom@8080000{ reg = <0x08080000 DT_SIZE_K(6)>; }; }; smbus2: smbus2 { compatible = "st,stm32-smbus"; #address-cells = <1>; #size-cells = <0>; i2c = <&i2c2>; status = "disabled"; }; smbus3: smbus3 { compatible = "st,stm32-smbus"; #address-cells = <1>; #size-cells = <0>; i2c = <&i2c3>; status = "disabled"; }; };