# Kconfig - XTENSA architecture configuration options
#
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0

menu "XTENSA Options"
	depends on XTENSA

menu "Specific core configuration"

config IRQ_OFFLOAD_INTNUM
	int "IRQ offload SW interrupt index"
	help
	  The index of the software interrupt to be used for IRQ offload.

	  Please note that in order for IRQ offload to work correctly the selected
	  interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL.

config XTENSA_OMIT_HIGH_INTERRUPTS
	bool "Skip generation of vectors for high priority interrupts"
	help
	  Setting this to y causes the interrupt vectors for "high
	  priority" Xtensa interrupts (those not masked by the EXCM bit
	  in PS) to be left ungenerated, so they can be handled by
	  application code instead.  Note that high priority interrupts
	  cannot safely be handled by C code anyway (they will interrupt
	  register window exceptions, which cannot be made reentrant, so
	  the code under the handler must not emit them), though some
	  devices might still want to use built-in handling for things
	  like watchdogs which do not need to return into interrupted
	  code.  Default is "n" for legacy compatibility. Consider
	  changing to "y" in the future.

config XTENSA_ASM2
	bool "New-style Xtensa context switch & interrupt layer"
	select USE_SWITCH
	help
	  This selects a new implementation of context switching and
	  interrupt handling.  Advantages are a much lower interrupt
	  overhead and smaller code size, and this scheme is required
	  for SMP.  Assumes/requires hardware that implements the
	  register window extension, however.

endmenu

config ARCH
	default "xtensa"

config SIMULATOR_XTENSA
	bool "Simulator Configuration"
	help
	  Specify if the board configuration should be treated as a simulator.

config SYS_CLOCK_HW_CYCLES_PER_SEC
	int "Hardware clock cycles per second, 2000000 for ISS"
	default 2000000
	range 1000000 1000000000
	help
	  This option specifies hardware clock.

config XTENSA_NO_IPC
	bool "Core has no IPC support"
	select ATOMIC_OPERATIONS_C
	help
	  Uncheck this if you core does not implement "SCOMPARE1" register and "s32c1i"
	  instruction.

config SW_ISR_TABLE
	bool "Enable software interrupt handler table"
	default y
	help
	  Enable an interrupt handler table implemented in software. This
	  table, unlike ISRs connected directly in the vector table, allow
	  a parameter to be passed to the interrupt handlers. Also, invoking
	  the exception/interrupt exit stub is automatically done.

config XTENSA_RESET_VECTOR
	bool "Build reset vector code"
	default y
	help
	  This option controls whether the initial reset vector code is built.
	  This is always needed for the simulator. Real boards may already
	  implement this in boot ROM.

config XTENSA_USE_CORE_CRT1
	bool "Use crt1.S from core"
	default y
	help
	  SoC or boards might define their own __start by setting this setting
	  to false.

config XTENSA_KERNEL_CPU_PTR_SR
	string
	default "MISC0"
	help
	  Specify which special register to store the pointer to
	  _kernel.cpus[] for the current CPU.

endmenu