/*
 * Copyright (c) 2020 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "skeleton.dtsi"
#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pcie/pcie.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "intel,elkhart_lake";
			d-cache-line-size = <64>;
			reg = <0>;
		};

	};

	dram0: memory@0 {
		device_type = "memory";
		reg = <0x0 DT_DRAM_SIZE>;
	};

	ibecc: ibecc {
	       compatible = "intel,ibecc";
	       status = "okay";
	};

	intc: ioapic@fec00000  {
		compatible = "intel,ioapic";
		#address-cells = <1>;
		#interrupt-cells = <3>;
		reg = <0xfec00000 0x1000>;
		interrupt-controller;
	};

	intc_loapic: loapic@fee00000  {
		compatible = "intel,loapic";
		reg = <0xfee00000 0x1000>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <1>;
	};

	pcie0: pcie0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "intel,pcie";
		ranges;

		ptm_root0: ptm_root0 {
			compatible = "ptm-root";

			vendor-id = <0x8086>;
			device-id = <0x4b38>;

			status = "okay";
		};

		uart0: uart0 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b28>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;
			status = "okay";
			current-speed = <115200>;
		};

		uart1: uart1 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b29>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
			current-speed = <115200>;
		};

		uart2: uart2 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b4d>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
			current-speed = <115200>;
		};

		uart_pse_0: uart_pse_0 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b96>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		uart_pse_1: uart_pse_1 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b97>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		uart_pse_2: uart_pse_2 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b98>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		uart_pse_3: uart_pse_3 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b99>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		uart_pse_4: uart_pse_4 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b9a>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		uart_pse_5: uart_pse_5 {
			compatible = "ns16550";

			vendor-id = <0x8086>;
			device-id = <0x4b9b>;

			reg-shift = <2>;
			clock-frequency = <1843200>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		smbus0: smbus0 {
			compatible = "intel,pch-smbus";
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b23>;
			interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c0: i2c0 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b78>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c1: i2c1 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b79>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c2: i2c2 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b7a>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c3: i2c3 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b7b>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c4: i2c4 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b4b>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c5: i2c5 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b4c>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c6: i2c6 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b44>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c7: i2c7 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4b45>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c_pse_0: i2c_pse_0 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4bb9>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c_pse_1: i2c_pse_1 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4bba>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c_pse_2: i2c_pse_2 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4bbb>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c_pse_3: i2c_pse_3 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4bbc>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c_pse_4: i2c_pse_4 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4bbd>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c_pse_5: i2c_pse_5 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4bbe>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		i2c_pse_6: i2c_pse_6 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			vendor-id = <0x8086>;
			device-id = <0x4bbf>;
			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "okay";
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		vtd: vtd@fed91000 {
			compatible = "intel,vt-d";

			reg = <0xfed91000 0x1000>;

			status = "okay";
		};


		uart1_fixed: uart@fe040000 {
			compatible = "ns16550";

			reg = <0xfe040000 0x1000>;
			reg-shift = <0>;

			clock-frequency = <1843200>;
			interrupts = <3 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		uart2_fixed: uart@fe042000 {
			compatible = "ns16550";

			reg = <0xfe042000 0x1000>;
			reg-shift = <0>;

			clock-frequency = <1843200>;
			interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
			current-speed = <115200>;
		};

		gpio_0_b: gpio@fd6e0700 {
			compatible = "intel,gpio";
			reg = <0xfd6e0700 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x0>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <24>;
			pin-offset = <0>;

			status = "okay";
		};

		gpio_0_t: gpio@fd6e08a0 {
			compatible = "intel,gpio";
			reg = <0xfd6e08a0 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x1>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <16>;
			pin-offset = <26>;

			status = "okay";
		};

		gpio_0_g: gpio@fd6e09a0 {
			compatible = "intel,gpio";
			reg = <0xfd6e09a0 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x2>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <24>;
			pin-offset = <42>;

			status = "okay";
		};

		gpio_1_v: gpio@fd6d0700 {
			compatible = "intel,gpio";
			reg = <0xfd6d0700 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x0>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <16>;
			pin-offset = <0>;

			status = "okay";
		};

		gpio_1_h: gpio@fd6d0800 {
			compatible = "intel,gpio";
			reg = <0xfd6d0800 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x1>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <24>;
			pin-offset = <16>;

			status = "okay";
		};

		gpio_1_d: gpio@fd6d0980 {
			compatible = "intel,gpio";
			reg = <0xfd6d0980 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x2>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <20>;
			pin-offset = <40>;

			status = "okay";
		};

		gpio_1_u: gpio@fd6d0ad0 {
			compatible = "intel,gpio";
			reg = <0xfd6d0ad0 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x3>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <20>;
			pin-offset = <61>;

			status = "okay";
		};

		gpio_1_vG: gpio@fd6d0c50 {
			compatible = "intel,gpio";
			reg = <0xfd6d0c50 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <28>;
			pin-offset = <85>;

			status = "okay";
		};

		gpio_3_s: gpio@fd6b0810 {
			compatible = "intel,gpio";
			reg = <0xfd6b0810 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x1>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <2>;
			pin-offset = <17>;

			status = "okay";
		};

		gpio_3_a: gpio@fd6b0830 {
			compatible = "intel,gpio";
			reg = <0xfd6b0830 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x2>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <24>;
			pin-offset = <25>;

			status = "okay";
		};

		gpio_3_vG: gpio@fd6b09b0 {
			compatible = "intel,gpio";
			reg = <0xfd6b09b0 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x3>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <4>;
			pin-offset = <49>;

			status = "okay";
		};

		gpio_4_c: gpio@fd6a0700 {
			compatible = "intel,gpio";
			reg = <0xfd6a0700 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x0>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <24>;
			pin-offset = <0>;

			status = "okay";
		};

		gpio_4_f: gpio@fd6a0880 {
			compatible = "intel,gpio";
			reg = <0xfd6a0880 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x1>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <24>;
			pin-offset = <24>;

			status = "okay";
		};

		gpio_4_e: gpio@fd6a0a70 {
			compatible = "intel,gpio";
			reg = <0xfd6a0a70 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x3>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <24>;
			pin-offset = <57>;

			status = "okay";
		};

		gpio_5_r: gpio@fd690700 {
			compatible = "intel,gpio";
			reg = <0xfd690700 0x1000>;
			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			group-index = <0x0>;
			gpio-controller;
			#gpio-cells = <2>;

			ngpios = <8>;
			pin-offset = <0>;

			status = "okay";
		};

		hpet: hpet@fed00000 {
			compatible = "intel,hpet";
			reg = <0xfed00000 0x400>;
			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
			interrupt-parent = <&intc>;

			status = "okay";
		};

		tco_wdt: tco_wdt@400 {
			compatible = "intel,tco-wdt";
			reg = <0x0400 0x20>;

			status = "disabled";
		};

		rtc: counter: rtc@70 {
			compatible = "motorola,mc146818";
			reg = <0x70 0x0D 0x71 0x0D>;
			interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
			interrupt-parent = <&intc>;
			alarms-count = <1>;

			status = "okay";
		};

	};
};