/*
 * Copyright (c) 2024 GARDENA GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <freq.h>

/ {
	chosen {
		zephyr,flash-controller = &flash;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m3";
			device_type = "cpu";
			clock-frequency = <20000000>;
			reg = <0>;
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	pinctrl: pinctrl {
		compatible = "silabs,si32-pinctrl";
		status = "okay";
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		pll0: pll0@4003b000 {
			compatible = "silabs,si32-pll";
			#clock-cells = <0>;
			reg = <0x4003b000>;
			status = "disabled";
		};

		clk_ahb: clk-ahb {
			compatible = "silabs,si32-ahb";
			#clock-cells = <0>;
			status = "disabled";
		};

		clk_apb: clk-apb {
			compatible = "silabs,si32-apb";
			#clock-cells = <0>;
			divider = <1>;
			clocks = <&clk_ahb>;
			status = "disabled";
		};
	};

	soc {
		dma: dma-controller@40036000 {
			compatible = "silabs,si32-dma";
			reg = <0x40036000 0x1000>;
			interrupts = <4 0>, <5 0>, <6 0>, <7 0>,
				     <8 0>, <9 0>, <10 0>, <11 0>,
				     <12 0>, <13 0>, <14 0>, <15 0>,
				     <16 0>, <17 0>, <18 0>, <19 0>;
			dma-channels = <16>;
			#dma-cells = <3>;
			status = "disabled";
		};

		flash: flash-controller@4002e000 {
			compatible = "silabs,si32-flash-controller";
			reg = <0x4002e000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@0 {
				compatible = "soc-nv-flash";
				write-block-size = <2>;
			};
		};

		usart0: usart@40000000 {
			compatible = "silabs,si32-usart";
			reg = <0x40000000 0x1000>;
			interrupts = <27 0>;
			clocks = <&clk_apb>;
			status = "disabled";
		};

		usart1: usart@40001000 {
			compatible = "silabs,si32-usart";
			reg = <0x40001000 0x1000>;
			interrupts = <28 0>;
			clocks = <&clk_apb>;
			status = "disabled";
		};

		gpio0: gpio@4002a0a0 {
			compatible = "silabs,si32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x4002a0a0 0xa0>;
		};

		gpio1: gpio@4002a140 {
			compatible = "silabs,si32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x4002a140 0xa0>;
		};

		gpio2: gpio@4002a1e0 {
			compatible = "silabs,si32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x4002a1e0 0xc0>;
		};

		gpio3: gpio@4002a320 {
			compatible = "silabs,si32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x4002a320 0xa0>;
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};