This driver is inspired from the w25qxxdv SPI NOR flash driver which was
already implementing the CFI (Common Flash Interface) for its purpose.
To handle other NOR flash a flash id table (as Linux do) which contains
the geometry for a few SPI NOR flash based on their JEDEC ID has been
introduced.
We currently support the following flash:
- W25Q80
- W25Q16
- W25Q32
- S25FL216K
- MX25UM512
The read and write functions are able to handle more then one page at a
time and return the number of bytes read or write.
Also because every NOR flash expect to disable the write protection
before writing or erasing, the write enable command is now part of the
write and erase functions.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Rewritten Xtensa CCOUNT driver along the lines of all the other new
drivers. The new API permits much smaller code.
Notably: The Xtensa counter is a 32 bit up-counter with a comparator
register. It's in some sense the archetype of this kind of timer as
it's the simplest of the bunch (everything else has quirks: NRF is
very slow and 24 bit, HPET has a runtime frequency detection, RISC-V
is 64 bit...). I should have written this one first.
Note also that this includes a blacklist of the xtensa architecture on
the tests/driver/ipm test. I'm getting spurious failures there where
a k_sem_take() call with a non-zero timeout is being made out of the
console output code in interrupt context. This seems to have nothing
to do with the timer; I suspect it's because the old timer drivers
would (incorrectly!) call z_clock_announce() in non-interrupt context
in some contexts (e.g. "expiring really soon"). Apparently this test
(or something in the IPM or Xtensa console code) was somehow relying
on that on Xtensa. But IPM is a Quark thing and there's no particular
reason to run this test there.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten driver along the lines of all the other new drivers,
implementing the new timer API. Structurally, the machine timer is an
up-counter with comparator, so it works broadly the same way HPET and
NRF do. The quirk here is that it's a 64 bit counter, which needs a
little more care.
Unlike the other timer reworks, this driver has grown by a few lines
as it used to be very simple. But in exchange, we get full tickless
support on the platform.
Fixes#10609 in the process (the 64 bit timer registers are unlatched
for sub-word transfers, so you have to use careful ordering).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reworked using the older hardware interface code, but with an
implementation of the new API only. Much smaller & simpler.
As yet, tested (manually) only on a nrf52_pca10056 board.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten along the lines of ARM SysTick. Implements only the new,
simplified API. MUCH smaller. Works with tickless pervasively. No
loss of functionality.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Many drivers won't need to implement z_clock_idle_exit() or
sys_clock_disable(). Make those weak stubs too.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a TICKLESS_CAPABLE kconfig variable which is used by the kernel to
select tickless mode's default automatically on drivers that support
it (rather than having to set the default per-board). Select it from
the ARM SysTick and Intel HPET drivers.
Also remove the old qemu_cortex_m3 default settings which this
replaces.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Qemu doesn't like tickless. By default[1] it tries to be realtime as
vied by the host CPU -- presenting read values from hardware cycle
counters and interrupt timings at the appropriate real world clock
times according to whatever the simulated counter frequency is. But
when the host system is loaded, there is always the problem that the
qemu process might not see physical CPU time for large chunks of time
(i.e. a host OS scheduling quantum -- generally about the same size as
guest ticks!) leading to lost cycles.
When those timer interrupts are delivered by the emulated hardware at
fixed frequencies without software intervention, that's not so bad:
the work the guest has to do after the interrupt generally happens
synchronously (because the qemu process has just started running) and
nothing notices the dropout.
But with tickless, the interrupts need to be explicitly programmed by
guest software! That means the driver needs to be sure it's going to
get some real CPU time within some small fraction of a Zephyr tick of
the right time, otherwise the computations get wonky.
The end result is that qemu tends to work with tickless well on an
unloaded/idle run, but not in situations (like sanitycheck) where it
needs to content with other processes for host CPU.
So, add a flag that drivers can use to "fake" tickless behavior when
run under qemu (only), and enable it (only!) for the small handful of
tests that are having trouble.
[1] There is an -icount feature to implement proper cycle counting at
the expense of real-world-time correspondence. Maybe someday we might
get it to work for us.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Newer, and much smaller driver written to the new timer API. Supports
all the features the old one did (including shutting off the clock
when clock_always_on is disabled), should be faster in practice, and
should be significantly more accurate due to the "lost cycle" trick
applied in z_clock_set_timeout().
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a dts binding for the Atmel WINC1500 WIFI chip. Update the
quark_se_c1000_devboard to utilize this binding as well as the wifi
sample app.
We now get all the GPIOs related to the Atmel WINC1500 from the device
tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Update a couple of labels generated from DTS used directly (not through
dts_fixups) in TI CC2650 system initialization code and a few drivers
for this SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Update a couple of labels generated from DTS used directly (not through
dts_fixups) in some serial drivers, to the reflect recent changes made
to the extracting script.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Specific code is present GPIO_DEVICE_INIT_STM32 in
GPIO_DEVICE_INIT_STM32 to handle LL_APB2_GRP1_PERIPH_AFIO bit.
Though, this bit is already included in device tree information,
in clocks property, 'bits' field, which carries for each GPIO,
both LL_APB2_GRP1_PERIPH_GPIOX and LL_APB2_GRP1_PERIPH_AFIO.
Hence, it is already taken into account in
CONFIG_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS and it is redundant
to handle it in GPIO_DEVICE_INIT_STM32 macro.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert the BMI160 to use Device Tree to get SPI and GPIO params instead
of Kconfig. Updated samples, tests, and arduino_101_sss board support
for this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The error check was wrong, if we could send the packet then
we free it. If sending fails, then let the caller to decide
what to do with the packet.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Add "Multicast Promiscuous Enabled" (RCTL_MPE) bit definition and
use it for the receive control register (RCTL) initialization.
Multicast needs to be enabled in order for IPv6 auto-configuration
to succeed.
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
The initial sequence was wrong and led to the missing interrupt
problem with netdev backends where the incoming traffic
appears immediately (tap).
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
Provide CONFIG macros for clocks bits and bus properties in fixup
files and use them to simplify logic in uart devices instanciation
code
Fixes#10448
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
CONFIG_ADC_DW_REPETITIVE and CONFIG_ADC_DW_DUMMY_CONVERSION aren't
defined anywhere so remove the associated code for these Kconfig
symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The channels assigned to the controller are reordered so that the ones
previously used and now available for other purposes have continuous
numbers. When the controller can take advantage of the pre-programmed
PPI channels (when TIMER0 is used as the event timer), the now free
channels are 0-4, when it cannot, it is the channel 0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Couple of findings which were revealed after changing
LOG_MODULE_REGISTER macro:
- missing semicolons after LOG_MODULE_REGISTER()
- missing LOG_LEVEL defines
- other
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Log configuration was included only in case NET_L2_IEEE802154 was
enabled. In case of open thread this is not the case.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Introduce new Kconfig option for selecting either slip or ethernet
connectivity to host.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Provide necessary error handling for `lis2dh_reg_read_byte` function
which might fail.
Also, use a common `status` variable to be used for storing the
error code.
Fixes#10590
Coverity-CID: 188733
Signed-off-by: Himanshu Jha <himanshujha199640@gmail.com>
The Kconfig variable for selecting neural network accelerator driver(s)
was changed from NEURAL_NET to NEURAL_NET_ACCEL
The CMakeLists.txt however, was not updated to use the updated variable
This commit updates CMakeLists.txt to include neural_net if
CONFIG_NEURAL_NET_ACCEL is defined.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
The information extracted from the device tree is now used to initialize
GPIO device instances. Up until now the GPIO device driver made no use
of this information. Actual instance creation is still controlled using
the Kconfig method. Missing GPIO device tree nodes were added in the
process for STM32L073, STM32F413 and STM32F373.
The information for gpio instance initialization has already been
present for supported STM32 SoCs but remained unused. Changes in the
device tree had no effect on GPIO functionality and was essentially
redundant. Using the device tree for hardware description seems
plausible and less painful than a myriad of defines in some SoC
description header.
The change was implemented under the assumption that current device
trees provide a correct description of the SoCs. Base register addresses
and RCC register bits were not explicitly checked for each device.
Manual tests were executed on:
- NUCLEO-F103RB
- STM32F429I-DISCO
- STM32F746G-DISCO
- NUCLEO-F767ZI
Manual tests consisted of blinky on different GPIOs and pins on each
board.
sanitycheck was executed for all STM32 based boards
Fixes: #10629
Signed-off-by: Martin Bertsche <martin72216@googlemail.com>
Update stm32f469i_disco configuration to match with
default configuration guidelines:
-Configure available connectors
-Update yaml file
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update stm32f723e_disco configuration to match with
default configuration guidelines:
-Configure available connectors
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update stm32f769i_disco configuration to match with
default configuration guidelines:
-Configure available connectors
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update stm32l496g_disco configuration to match with
default configuration guidelines:
-Deactivate features by default
-Configure available connectors
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update disco_l475_iot1 configuration to match with
default configuration guidelines:
-Deactivate features by default
-Configure available connectors
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename USB_{DBG,ERR,INF,WRN} into LOG_{DBG,ERR,INF,WRN}. This driver has
been missed from PR #11001 as it has been committed after.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Check for case where host == NULL but service != NULL
could have resulted later in a NULL dereference.
Coverity-CID: 189516
Fixes#11090
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Savinay Dharmappa