A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.
As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This patch adds the RDC (Resource Domain Controller) peripheral
permissions settings for the i.MX applications cores (Cortex A9 on
i.MX6 and Cortex A7 on i.MX7).
This will enable both Linux (on application's core) and Zephyr (on M4
core) to share the peripherals and coexist.
The settings are defined at devicetree level and applied in the soc.c.
A complete solution should involve the SEMA4 to control the peripherals
access and prevent resource deadlocking and misusage.
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
The mcux sim clock control driver was originally designed to pass
through the clock subsystem value from dts to the mcux CLOCK_GetFreq()
function. This assumed that the values in
include/dt-bindings/clock/kinetis_sim.h matched the enumeration in
fsl_clock.h, which is true for the coresys, platform, and bus clocks.
However, the low-power oscillator (LPO) clock has a different values in
k64 vs. kw2xd, therefore we must update the clock_control driver to
parse the value from dts and convert it to the fsl_clock.h enumeration.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Create a dt-bindings/gpio.h file.
Bindings definitions are extracted from existing gpio.h.
gpio dt-bindings file is required because existing gpio.h file could
not be parsed by dts parser.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds device tree bindings for the Kinetis System Integration Module
(SIM), and defines peripheral source clocks (e.g., system clock or bus
clock) and clock gates for all Kinetis SoCs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Clarify that the clock-frequency is the bitrate at boot and introduce
defines that .dts files can use to set the clock-frequency.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32 pin configuration comments where offset by 4 bits.
Fix this issue and make pin configuration settings
easier to read.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add needed uart pinctrl configuration in pinmux node.
This is done thanks to <soc>-pinctrl.dtsi file matching
the <soc>.dtsi files
Populate stm32 f4 based boards dts files with references
to uart pinctrl nodes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add pinmux yaml file and bindings before introduction
of pinmux node in stm32 soc device tree files
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add "clocks" property on u(s)arts nodes on stm32 socs
Add a dt clocks binding file and rework clock_control
header file include new device tree binding file.
include/dt-bindings folder is introduced as dt-bindings
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Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Charles E. Youse