Many Kinetis SoCs contain an Oscillator (OSC) module and a Multipurpose
Clock Generator (MCG) module to configure clocks. Adding options to
configure these modules for PLL operation with different external
oscillator frequencies, which can vary across boards. More options may
be added later to support other clocking modes such as FLL.
Jira: ZEP-715
Change-Id: Ia121cc5b464d7e681883507bd756d331a8abd6ef
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add Kinetis SoC family and rename fsl_frdm_k64f to mk64f12.
This will allow adding new SoCs of the same family and the reuse of code
among SoCs of the family and series.
Change-Id: Iea1a663aef7ce0487f147bdd36f668bebe80deb5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Making pinmux depend on GPIO breaks many tests and configurations
when running on real hardware. This should be added as local
configuration in the defconfig instead.
Change-Id: Ibbf1c9a3428ed692937383bf85218b0c120cbe44
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Shorten the name and remove the vendor prefix. No need to add
vendor to board names.
Change-Id: I68d441121c4034276706da63d7e5420ddf317149
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Maureen Helm