Commit Graph

74 Commits

Author SHA1 Message Date
Andrew Boie 956089bcae xtensa: add config for toolchain version
Use TOOLCHAIN_VARIANT to indicate what XCC toolchain release
to use.

Set a reasonable default for the RG-2016.4 toolchain release.
D_108mini, D_212GP, D_233L are only in RF-2016.4, set that
appropriately.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-18 07:18:36 -04:00
Andrew Boie 286a2c875f xtensa: fix XCC build
XCC doesn't recognize the "I" compiler constraint but GCC does. Switch
to "i" which is understood by both.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-15 13:33:12 -04:00
Andrew Boie 5dcb279df8 debug: add stack sentinel feature
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.

This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 15:14:41 -04:00
Andrew Boie 51df312abc xtensa: merge crt1-*.S
We had two assembly files to prepare for entry into C domain,
one intended for the simulator and one intended for real boards.

- Both files merged into a single crt1.S for either simulated or real
  targets
- Extra logic to populate command line arguments from simulator removed,
  we don't use it.
- BSS zeroing logic from crt1-boards.S used
- Reference to missing reset-unneeded.S removed
- exit() implementation moved to fatal.c, now invokes a kernel panic
  if we are not running under the simulator

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-12 12:56:12 -04:00
Andrew Boie b7aa6b7bd0 xtensa: optionally build reset vector code
In real-world use-cases this isn't always needed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-12 12:56:12 -04:00
Anas Nashif f628c12b04 xtensa: rename SOC_SAMPLE_CONTROLLER
SOC_SAMPLE_CONTROLLER option name is too generic, make it Xtensa
specific to avoid confusion.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-12 07:00:04 -04:00
Andrew Boie d26cf2dc33 kernel: add k_thread_create() API
Unline k_thread_spawn(), the struct k_thread can live anywhere and not
in the thread's stack region. This will be useful for memory protection
scenarios where private kernel structures for a thread are not
accessible by that thread, or we want to allow the thread to use all the
stack space we gave it.

This requires a change to the internal _new_thread() API as we need to
provide a separate pointer for the k_thread.

By default, we still create internal threads with the k_thread in stack
memory. Forthcoming patches will change this, but we first need to make
it easier to define k_thread memory of variable size depending on
whether we need to store coprocessor state or not.

Change-Id: I533bbcf317833ba67a771b356b6bbc6596bf60f5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 20:24:22 -04:00
Anas Nashif 09b239102a xtensa: xt-sim: mark it as a board with simulator features
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-11 16:51:56 -04:00
Max Filippov 4b8419e420 xtensa: drop references to C library
C library is not actually used by the xtensa port, we only need the
'exit' function. Implement 'exit' in crt1-* and drop remaining
references to the C library.

Change-Id: I8a562363956b4755a6b5baee7acf3726485e5ce3
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Max Filippov 0538dc1a1c xtensa: make sample_controller runnable on QEMU
Add QEMU_CPU_TYPE for the sample_controller, so that zephyr image could
be run on QEMU with sample_controller core.

Change-Id: Id9e97a43c4b7921142289dcf97ff782993ca0463
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Max Filippov 6a89999787 xtensa: use inline assembly instead of XT_* macros
XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc
does not have any of these intrinsics. Replace XT_* macros with inline
assembly or provide gcc-compatible definitions.

Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Andrew Boie f57e79b6d5 xtensa: remove Kconfig.cores
This file is no longer used by the build system.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
Andrew Boie 99c89e17e3 xtensa: fix coprocessor save area
A bad rebase of a patch that moved these defines around
unintentionally reverted a necessary change to the coprocessor
save area.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
Mazen NEIFER 51eb081311 xtensa port: Fixed crash on interrupt handlers when logger is enabled.
This fixes ZEP-1955. The issue was that the interrupt stack frame only
allocates 4 registers. This means that if any window overflow happens,
only 4 registers can be saved. This implies that the interrupt handler
can not call functions other than using call4. If this rule is not
honored, then it will result in the registers being overwriting other
context information and thus a stack corruption.

The fix consists on using call4 for calling even t logger function,
which is by the way more optimal as the interrupt handler does not need
to save more than 4 registers when these functions are called.

Issue: ZEP-1955

Change-Id: Iacea626443d1d61d95a52253ac8ff15fc3722d2c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-28 15:49:01 +00:00
Ramesh Thomas 62eea121b3 kernel: tickless: Rename _Swap to allow creation of macro
Future tickless kernel patches would be inserting some
code before call to Swap. To enable this it will create
a mcro named as the current _Swap which would call first
the tickless kernel code and then call the real __swap()

Jira: ZEP-339
Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-27 13:46:26 +00:00
Andrew Boie 73abd32a7d kernel: expose struct k_thread implementation
Historically, space for struct k_thread was always carved out of the
thread's stack region. However, we want more control on where this data
will reside; in memory protection scenarios the stack may only be used
for actual stack data and nothing else.

On some platforms (particularly ARM), including kernel_arch_data.h from
the toplevel kernel.h exposes intractable circular dependency issues.
We create a new per-arch header "kernel_arch_thread.h" with very limited
scope; it only defines the three data structures necessary to instantiate
the arch-specific bits of a struct k_thread.

Change-Id: I3a55b4ed4270512e58cf671f327bb033ad7f4a4f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-26 16:29:06 +00:00
Mazen NEIFER e87564bd88 xtensa port: Removed XRC_D2PM SoC configuration
This SoC, in its default configuration, does not have any SW IRQ below
the EXCM level. This make it unsuitable to use irq_offload() and thus
almost untestable.

Decision was made to remove this configuration in favorof custom one
XRC_D2PM_5swIrq, which is the same core but with additional 4 SW IRQs
of level 1 and an additional timer.

Issue: ZEP-2029

Change-Id: Iee4f8346aa9d610e14898444f78d28ef0ac4cef2
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-26 09:50:44 +00:00
Mazen NEIFER 35a48decfa xtensa port: Fixed compilation error introduced by recent changes.
The error was introduced by
    b8823c4efd

Change-Id: Ibf930107a7a690e0cb0851b7c247d524e3cb89e5
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-24 20:41:46 +00:00
Andrew Boie cdb94d6425 kernel: add k_panic() and k_oops() APIs
Unlike assertions, these APIs are active at all times. The kernel will
treat these errors in the same way as fatal CPU exceptions. Ultimately,
the policy of what to do with these errors is implemented in
_SysFatalErrorHandler.

If the archtecture supports it, a real CPU exception can be triggered
which will provide a complete register dump and PC value when the
problem occurs. This will provide more helpful information than a fake
exception stack frame (_default_esf) passed to the arch-specific exception
handling code.

Issue: ZEP-843
Change-Id: I8f136905c05bb84772e1c5ed53b8e920d24eb6fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 10:31:49 -04:00
Kumar Gala 96ee45df8d kernel: refactor thread_monitor_init into common code
We do the same thing on all arch's right now for thread_monitor_init so
lets put it in a common place.  This also should fix an issue on xtensa
when thread monitor can be enabled (reference to _nanokernel.threads).

Change-Id: If2f26c1578aa1f18565a530de4880ae7bd5a0da2
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:42 +00:00
Kumar Gala b8823c4efd kernel: Refactor common _new_thread init code
We do a bit of the same stuff on all the arch's to setup a new thread.
So lets put that code in a common place so we unify it for everyone and
reduce some duplicated code.

Change-Id: Ic04121bfd6846aece16aa7ffd4382bdcdb6136e3
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:42 +00:00
David B. Kinder 36bb36475f spell: fix Kconfig help typos: /arch
Fix misspellings in Kconfig help text

Change-Id: I2a753b57107f09073eb84ac757ac1e180ae89349
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-21 12:30:42 +00:00
Kumar Gala bf53ebf2c8 arch: convert to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point.  Fixup a few of the PRI formatters so we build with newlib.

Jira: ZEP-2051

Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 12:08:12 +00:00
Kumar Gala 789081673f Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t.  This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.

We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.

We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.

Jira: ZEP-2051

Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-20 16:07:08 +00:00
Mazen NEIFER 01e9646638 xtensa port: Clear the CP descriptor of new created thread.
This commit should fix the concern about uninitialized memory of main
thread that was raised in https://gerrit.zephyrproject.org/r/#/c/12920/

The issue is more general, if it happens that the content of the
CPENABLE flag of any thread is set then any other thread using the CP
may cause a memory corruption.

I'd prefer to avoid the issue by initializing the CP descriptor to 0.
The descriptor itself is few words. We set them to 0 up to CP_ASA, which
is set to a real value.

As the dummy thread instantiated at the kernel startup does not use CP,
there is no CP area in its thread memory buffer. However it is mandatory
that it have the CP descriptor and that cpEnable in that descripot is
set to null. This is ensured by adding XT_CP_DESCR_SIZE to
_K_THREAD_NO_FLOAT_SIZEOF.

Change-Id: I6a36b5b363600ea1e6d98ab679981182b2b5a236
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-20 16:01:55 +00:00
Max Filippov 59926490be xtensa: move #include <linker/common-*.ld> up
Move linker/common-rom.ld between .rodata sections so that it's together
with other immutable data.
Move linker/common-ram.ld before the .bss section, so that .bss does not
appear between data sections, which had two consequences:
- there's a .bss-sized gap in the ELF image, and
- PHDR segment that covers .bss overlaps the segment that covers .data,
  resulting in the following xt-run warning:

  ( [ sample_controller ] load_bfd ) *WARNING* Executable segment
    [ 60004d60, 600079a7 ] overlaps an existing executable segment

Change-Id: I2db46f4656e240016fe60883057cc000b6377180
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-04-20 16:01:18 +00:00
Anas Nashif 8df439b40b kernel: rename nanoArchInit->kernel_arch_init
Change-Id: I094665e583f506cc71185cb6b8630046b2d4b2f8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-19 10:59:35 -05:00
Kumar Gala fded58d2af Revert "arch: Convert formatter strings to use PRI defines"
This reverts commit da8bff6b20.

We revert this as we intent to move away from {u}int{8,16,32,64}_t types
to our own internal types for sized variables so we shouldn't need the
PRI macros anymore.

Change-Id: Ibb1fae7500bddb4772b8830d497a0e5f78b44bcc
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-19 10:50:51 -05:00
Kumar Gala da8bff6b20 arch: Convert formatter strings to use PRI defines
To allow for various libc implementations (like newlib) in which the way
various {u}int{8,16,32}_t types are defined vary between both libc
implementations and across architectures we need to utilize the PRI
defines.

Change-Id: Ic4e65db52c8d693228cf80584283d4d06e68b5ad
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-17 11:09:36 -05:00
Max Filippov a0fa4f3265 xtensa: use -mlongcalls instead of --longcalls
gcc only understands -mlongcalls form of this option, xcc understands
both. Use -mlongcalls for building with both xcc and gcc.

Change-Id: I93f65ccbc97429ae564f1986120b37ce205ee38c
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-04-13 20:33:28 +00:00
Mazen NEIFER a6e0404983 xtensa port: Fixed crash on startup on CP enabled cores
The issue was that cpStack was changed to a memory buffer by commit
https://gerrit.zephyrproject.org/r/#/c/12816
However the assembly code was expecting it to be a pointer and thus
issuing an indirection, that leads to wrong addresses.

The fix removed this unnecessary indirection and thus the inherent
invalid memory access exception.

Issue: ZEP-1997
Change-Id: I843f049212f2d116a01b05367a284209f463a5e7
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-13 11:54:49 -07:00
Andrew Boie 11ee791b32 xtensa: build similar to other Zephyr arches
* CONFIG_SOC is now properly set and we do not need a separate
  XTENSA_CORE build variable

* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed

* There is no default SOC selection, it is now done explicitly in
  the board's defconfig

* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
  uppercase> to conform to established style.

Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 12:42:06 +00:00
Andrew Boie b037d4d54c xtensa: fix tickless idle build
_power_save_idle_exit() was removed long ago. All arches now just
call _sys_power_save_idle_exit() if PM is enabled.

Change-Id: I9cce3eecc8cbf1cbce15a355be420e747fb978de
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-12 16:31:46 +00:00
Mazen NEIFER cc8ffbdb44 Xtensa port: Moved coporcessor context area inside struct _k_thread
The CP context area was before on the bottom of the stack just
after the thread descriptor. Now it is moved inside the thread
descriptor to support some kind of memory protection.

Change-Id: Id3ebeaecfd9c2475899713fdc8da583a1f9121f9
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-11 00:05:27 +00:00
Anas Nashif b84dc2e124 kernel: remove all remaining references to nanokernel
Change-Id: I43067508898bc092879f7fe9d656ccca6fd92ab2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:10 +00:00
Anas Nashif d7bc60f096 kernel: remove remaining microkernel references
Change-Id: Ie648dbaaf714316c21395bd43e555618013dbd19
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:05 +00:00
Andrew Boie 5c9f7e28a1 xtensa: remove legacy kernel cruft
fibers/tasks are now just threads and we should not be using
struct *tcs any more.

Change-Id: Iee5369abcc66b4357a0c75537025fe8edb0ffbb4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-03 16:40:48 +00:00
Andrew Boie 42562b9367 xtensa: fix numerous checkpatch issues
Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:03 -08:00
Mazen NEIFER fb5299cd4a Xtensa port: Removed trailing spaces and unused macros. Reformatted comments.
Change-Id: I7f3fcba5d78c153c9b2830982e3ed6d5a1150c78
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:03 -08:00
Mazen NEIFER ff0828faf3 Xtensa port: Fixed compilation errors caused by last rebase on master.
Change-Id: If2896bcce26652ded2059a11620370e34f98d1e4
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER 74ff1092d4 Xtensa port: Prevent preemption of locked threads.
When an IRQ is serviced, the ISR dispatcher will check for any new thread in
the ready queue and switch to it. However, if the current thread is marked as
non preemptable due to _kernel.current->base.preempt > _NON_PREEMPT_THRESHOLD
then we should not switch to another one.

Change-Id: Icdc08105cc6433da479bb95265710462a0f37c0b
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Andrew Boie 53f66d0bf7 xtensa: remove nonexistent offset
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Andrew Boie de099439b1 xtensa: fix build warning if no coprocessors present
Change-Id: Ib754795eff073500a38e4b383268b4f90c1763a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER 3b95e3d729 Xtensa port: Added support for sample_controller core and set is as default.
This core is not depreciated and compilationfor it is even faster than D_233L.

Change-Id: I6b8149ca9e879770c3ed0973ffb9304e2e3c8d8d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Andrew Boie 9249f876a9 xtensa: cleanup fatal error handling
1) Fatal errors now all go through _SysFatalErrorHandler. When the
simulator is used, only the death of 'essential' threads will result
in the simulator exiting; some test cases that test exceptions may
actually expect a thread to terminate abnormally.

2) The human readability of the exception errors is improved.

Change-Id: I77f57ea0eae15b0c55237681b959cd21e3fe8c1c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER b06115aa7c Xtensa port: Fixed memory corruption in interrupt handler exit function.
The a3 register was supposed to hold the _thread pointer but it seems that it
does not in all cases. Safe to restore it from _kernel structure.

Change-Id: Ie2ff6c3faf0fe70de4c5877ab59433d0c165145b
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:01 -08:00
Mazen NEIFER 884005673c Xtensa port: Set Swap function result to -EAGAIN.
Change-Id: I70a651012d5da873c98f6b13ada5e80e67e18e0c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER 51efd6d4dc Xtensa port: Moved coprocessor stack area on bottom of stack, just after TCS.
This change should allow threads that do not access coprocessor to safely
overflow on the coprocessor save area without any issue.

Change-Id: Ic2acd20b60b6bef0b7feeb8cfb54d548eba892f0
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER ef098bf410 Xtensa port: Restore interrupted context the same way as premption resume.
This was a kind of optimization that save few cycles in the cost of code
duplication. However the path where we resume from interrupt withouch changing
the running thread is buggy and leads to many tests to fail. For now I'd prefer
to remove this optimization and have a working port. Later, once everything is
OK, I'll have time to optimize things.

Change-Id: I7af58f383848d157b9f3b3fbeceede3e83f9ce61
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER b978c70338 Xtensa port: Removed duplicate code and fixed update of current thread pointer.
Having duplicate code leads always to this kind of situation where a bug is
fixed in one place and not in the other. This bug of updating current thread
pointer was already fixed before in the Swap function, but not in the interrupt
handler.

Change-Id: I466aea2d35382446c5c82fe775ada31f0bd19492
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00