We have been building offsets.o in the include directory, this
is wrong.
Change-Id: I22e785413158117e1cdfa8353bd7f4d022fae0ac
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Makefile.inc duplicates many of the existing targets in Makefile.
Instead of duplication, pass all none local targets to Makefile
and implement only those needed locally.
Change-Id: I1e923dd398a138543fa676ab67570b630c75d7ea
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This will allow building of external components and linking
them at the end of the build process to the main kernel.
add a Makefile.app to the project directory with the required
targets, for example
Makefile.app:
KBUILD_ZEPHYR_APP := /tmp/libapp.a
/tmp/libapp.a:
@touch /tmp/libapp.a
Change-Id: If2ba6b3ee59023acc5f85c5701b65c4d096d5059
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
See
https://groups.google.com/forum/#!topic/ia32-abi/cn7TM6J_TIg
for more details.
• Support IA32 without FPU.
• Minimum ISA: Pentium ISA without x87 FPU instructions.
• Don't allow mixing i386 object files with Intel MCU object files.
• Support floating point with software emulation:
a. Long double is the same as double.
b. Use __float80 for 80-bit double.
• Minimize memory footprint:
a. Code size
b. Data size
c. Stack size
Here is the draft of Intel MCU psABI. The differences from IA32
psABI are
1. The minimum instruction set is Intel Pentium ISA minus instructions
for x87 floating point unit.
2. There are no x87 floating point registers.
3. There are no vector registers.
4. Segment registers are optional.
5. Support for TLS relocations are optional.
6. Scalar types larger than 4 bytes are aligned to 4 bytes.
7. There are no vector types.
8. _Decimal32, _Decimal64, and _Decimal128 types are optional.
9. long double type is the same as double.
10. float, double and long double types are passed and returned in
general purpose registers.
11. _Decimal32 and _Decimal64 types are passed in general purpose
registers.
12. Aggregate types no larger than 8 bytes are passed and returned
in general purpose registers.
13. Stack is 4-byte aligned.
14. The auxiliary vector support is optional.
15. Register %edx has undefined value at process entry.
16. New ELF machine code: EM_IAMCU.
17. New predefined C/C++ pre-processor symbols: __iamcu and __iamcu__
Change-Id: I6a0c45ad22d8f710b6f37a041aaa2fc1bf0b1c39
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Restore original behaviour from before moving to kbuild
Change-Id: I299ad25cf39378b2537e0791cce65f077c5d1c08
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove excessive use of zephyr and use a more generic
terminology where possible.
Change-Id: Ida8916765dbe824f63d7a4cedba60b35d14aee55
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Alexandre dAlton