Providing the right settings through Galileo's Kconfig.
Change-Id: Ia5339eb90cb98d7dde3be0493bcfd9a6b6db60ed
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add Kconfig option to specify how interrupt is triggered for SPI.
Also enabling such support for Galileo platform.
Change-Id: Id3112d100089197940f826b827493174d0f22669
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is specific to Galileo board where its SPI port 0 needs to setup
the CS pin through a GPIO pin.
Change-Id: I9df6f7144a96bcd10f61fc7d057f89caa0e599d1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.
Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This macro is legacy from an early implementation of the init system
before the pure level was split into early and late phases remove it
now to avoid confusion going forward.
Change-Id: I6720874c840c9e14888fd6f411a8182e7420ca29
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
The code fragment to bind the instances of the SPI driveri is not
platform specific but is driver specific.
All the information required to bind a driver instance comes from
CONFIG_ variables. Having the binding code with the driver code
avoids duplicating the code fragments in each platform where the
driver may be used.
Change-Id: Iff40227e3e25d431ae870d585445971f35d934dd
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Or then the controller will spin around requesting to get its fifo
filled-in though it's unnecessary.
Change-Id: I81e7c483345236dee7691c3e780b1b06d6b2d0f8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Handle the new error callback type, a ROR interrupt is irrecoverable.
- Removing the fifo pre-fill: this should never be done that way. It's
up to the controller to request via an interrupt to get its fifo
filled-in. (TFS bit on SSSR register is the one requesting such
filling)
- Disabling the controller once completed (following transfer will
re-enable it)
- Removing useless debugging info
Change-Id: I466a8efb65a41f3315a6a36e10ea519d0c4b01e9
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without it, it won't go through a pci scan, and will just trust the
pre-set information for the bus/dev/function to enable the memory
mapped registers.
Change-Id: Ica9156be541619dce9684dd45f70e05b69782a7c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will make code that use it not too crowded with #ifdef #endif
Change-Id: Iec0fa662445b1cefdc7c64d9483e1ae483106a90
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such controllers are found in Quark's X1000 series, and thus are found
on Galileo boards v1 and v2.
Change-Id: Ib71486c9f27de1b6c48ce3cb3dd138d69833c2ea
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Tomasz Bursztyka