3 Commits

Author	SHA1	Message	Date
Kumar Gala	5ef93aa639	tests: kernel: interrupt: Exclude platforms test isnt valid on ... The test assumes that the last to IRQ numbers will be free, this isn't a valid assumption and now that we detect multiple ISRs registering for the some IRQ line, we see failures because of this assumption on some platforms. Exclude those platforms from this test for the time being. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>	2019-02-07 15:58:43 -05:00
Anas Nashif	d3ed3f11fa	tests: interrupt: disable riscv32 ... This is a new test and we have riscv32 failing on that all of the sudden. Disabling while we look into it and identify if that is a testcase issue or not. Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2018-10-16 21:27:23 -04:00
Ajay Kishore	2a103ea674	tests: add tests to validate interrupt nesting feature ... This test is intended to verify the interrupt nesting. Interrupt nesting feature allows an ISR to be preempted in mid-execution if a higher priority interrupt is signaled. The lower priority ISR resumes execution once the higher priority ISR has completed its processing. Signed-off-by: Ajay Kishore <ajay.kishore@intel.com>	2018-10-10 19:59:47 -04:00